ia-32_volume1_basic-arch

sw denormalmask excenv statusflagdenormaloperand

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Unformatted text preview: break; default: ... } } MAXPS: MAXSS: MINPS: MINSS: E-32 Vol. 1 INDEX Numerics 128-bit packed byte integers data type, 4-11, 11-5 packed double-precision floating-point data type, 4-11, 11-5 packed doubleword integers data type, 4-11 packed quadword integers data type, 4-11 packed SIMD data types, 4-11 packed single-precision floating-point data type, 4-11, 10-8 packed word integers data type, 4-11, 11-5 16-bit address size, 3-11 operand size, 3-11 286 processor, 2-1 32-bit address size, 3-11 operand size, 3-11 64-bit packed byte integers data type, 4-10, 9-4 packed doubleword integers data type, 4-10 packed doubleword integers data types, 9-4 packed word integers data type, 4-10, 9-4 64-bit mode sub-mode of IA-32e, 3-2 address calculation, 3-12 address size, 3-25 address space, 3-6 BOUND instruction, 7-25 branch behavior, 6-11 byte register limitation, 3-17 CALL instruction, 6-12, 7-24 canonical address, 3-13 CMPS instruction, 7-27 CMPXCHG16B instruction, 7-7 data types, 7-2 DEC instruction, 7-11 decimal arithmetic instructions, 7-14 default operand and address sizes, 3-2 exceptions, 6-19 far pointer, 4-8 feature list, 2-22 GDTR register, 3-6 IDTR register, 3-6 INC instruction, 7-11 instruction pointer, 3-12, 3-24 instructions introduced, 5-31 interrupts, 6-19 introduction, 2-22, 3-2, 7-2 IRET instruction, 7-25 I/O instructions, 7-28 JCC instruction, 6-12, 7-24 JCXZ instruction, 6-12, 7-24 JMP instruction, 6-12, 7-24 LAHF instruction, 7-30 LDTR register, 3-6 legacy modes, 2-22 LODS instruction, 7-27 LOOP instruction, 6-12, 7-24 memory models, 3-11 memory operands, 3-28 MMX technology, 9-2 MOVS instruction, 7-27 MOVSXD instruction, 7-10 near pointer, 4-8 operand addressing, 3-32 operand size, 3-25 operands, 3-28 POPF instruction, 7-30 promoted instructions, 3-2 PUSHA, PUSHAD, POPA, POPAD, 7-9 PUSHF instruction, 7-30 PUSHFD instruction, 7-30 real address mode, 3-11 register operands, 3-28 REP prefix, 7-27 RET instruction, 6-12, 7-24 REX prefix, 3-2, 3-16, 3-25 RFLAGS register, 7-30 RIP register, 3-12 RIP-relative addressing, 3-24, 3-32 SAHF instruction, 7-30 SCAS instruction, 7-27 segment registers, 3-20 segmentation, 3-11, 3-30 SSE extensions, 10-4 SSE2 extensions, 11-4 SSE3 extensions, 12-1 SSSE3 extensions, 12-1 stack behavior, 6-5 STOS instruction, 7-27 TR register, 3-6 x87 FPU, 8-2 See also: IA-32e mode, compatibility mode 8086 processor, 2-1 8088 processor, 2-1 A AAA instruction, 7-13 AAD instruction, 7-13 AAM instruction, 7-13 AAS instruction, 7-13 AC (alignment check) flag, EFLAGS register, 3-23 Access rights, segment descriptor, 6-9, 6-14 ADC instruction, 7-11 ADD instruction, 7-11 Vol. 1 INDEX-1 INDEX ADDPD instruction, 11-8 ADDPS instruction, 10-11 Address size attribute code segment, 3-24 description of, 3-24 of stack, 6-3 Address sizes, 3-11 Address space 64-bit mode, 3-2, 3-6 compatibility mode, 3-2 overview of, 3-3 physical, 3-8 Addressing modes assembler, 3-32 base, 3-30, 3-31, 3-32 base plus displacement, 3-31 base plus index plus...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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