Unformatted text preview: X -- Pointer to data in the DS segment ECX -- Counter for string and loop operations EDX -- I/O pointer ESI -- Pointer to data in the segment pointed to by the DS register; source pointer for string operations EDI -- Pointer to data (or destination) in the segment pointed to by the ES register; destination pointer for string operations Vol. 1 3-15 BASIC EXECUTION ENVIRONMENT ESP -- Stack pointer (in the SS segment) EBP -- Pointer to data on the stack (in the SS segment) As shown in Figure 3-5, the lower 16 bits of the general-purpose registers map directly to the register set found in the 8086 and Intel 286 processors and can be referenced with the names AX, BX, CX, DX, BP, SI, DI, and SP. Each of the lower two bytes of the EAX, EBX, ECX, and EDX registers can be referenced by the names AH, BH, CH, and DH (high bytes) and AL, BL, CL, and DL (low bytes). 31 General-Purpose Registers 8 7 16 15 AH BH CH DH BP SI DI SP AL BL CL DL 0 16-bit 32-bit AX BX CX DX EAX EBX ECX EDX EBP ESI EDI ESP Figure 3-5. Alternate General-Purpose Register Names 220.127.116.11 General-Purpose Registers in 64-Bit Mode In 64-bit mode, there are 16 general purpose registers and the default operand size is 32 bits. However, general-purpose registers are able to work with either 32-bit or 64-bit operands. If a 32-bit operand size is specified: EAX, EBX, ECX, EDX, EDI, ESI, EBP, ESP, R8D - R15D are available. If a 64-bit operand size is specified: RAX, RBX, RCX, RDX, RDI, RSI, RBP, RSP, R8-R15 are available. R8D-R15D/R8-R15 represent eight new general-purpose registers. All of these registers can be accessed at the byte, word, dword, and qword level. REX prefixes are used to generate 64-bit operand sizes or to reference registers R8-R15. 3-16 Vol. 1 BASIC EXECUTION ENVIRONMENT Table 3-2. Addressable General Purpose Registers
Register Type Byte Registers Word Registers Doubleword Registers Quadword Registers Without REX AL, BL, CL, DL, AH, BH, CH, DH AX, BX, CX, DX, DI, SI, BP, SP EAX, EBX, ECX, EDX, EDI, ESI, EBP, ESP N.A. With REX AL, BL, CL, DL, DIL, SIL, BPL, SPL, R8L - R15L AX, BX, CX, DX, DI, SI, BP, SP, R8W - R15W EAX, EBX, ECX, EDX, EDI, ESI, EBP, ESP, R8D - R15D RAX, RBX, RCX, RDX, RDI, RSI, RBP, RSP, R8 - R15 In 64-bit mode, there are limitations on accessing byte registers. An instruction cannot reference legacy high-bytes (for example: AH, BH, CH, DH) and one of the new byte registers at the same time (for example: the low byte of the RAX register). However, instructions may reference legacy low-bytes (for example: AL, BL, CL or DL) and new byte registers at the same time (for example: the low byte of the R8 register, or RBP). The architecture enforces this limitation by changing high-byte references (AH, BH, CH, DH) to low byte references (BPL, SPL, DIL, SIL: the low 8 bits for RBP, RSP, RDI and RSI) for instructions using a REX prefix. When in 64-bit mode, operand size determines the number of valid bits in the destination general-purpose register: 64-bit operands generate a 64-bi...
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- Winter '11
- X86, Intel corporation, 64-bit mode, fpu floating-point exception, FPU Control Instructions