ia-32_volume1_basic-arch

Ia-32_volume1_basic-arch

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Unformatted text preview: 3 FSTP instruction, 8-23 FSTSW/FNSTSW instructions, 8-6, 8-32 FSUB instruction, 8-25 FSUBP instruction, 8-25 FSUBR instruction, 8-25 FSUBRP instruction, 8-25 FTST instruction, 8-9, 8-27 FUCOM instruction, 8-26 FUCOMI instruction, 8-10, 8-26 FUCOMIP instruction, 8-10, 8-26 FUCOMP instruction, 8-26 FUCOMPP instruction, 8-9, 8-26 FXAM instruction, 8-7, 8-27 FXCH instruction, 8-23 FXRSTOR instruction, 5-13, 8-17, 10-20, 11-34 FXSAVE instruction, 5-13, 8-17, 10-20, 11-34 FXTRACT instruction, 8-25 FYL2X instruction, 8-31 FYL2XP1 instruction, 8-31 data types operated on, 7-1, 7-2 description of, 7-1 origin of, 7-1 programming with, 7-1 summary of, 5-2, 7-3 GS register, 3-17, 3-19 H HADDPD instruction, 5-27, 12-6 HADDPS instruction, 5-26, 12-5 Hexadecimal numbers, 1-6 Horizontal processing model, 12-2 HSUBPD instruction, 5-27, 12-6 HSUBPS instruction, 5-26, 12-6 HT Technology first processor, 2-4 implementing, 2-19 introduction, 2-18 I IA-32 architecture history of, 2-1 introduction to, 2-1 IA-32e mode introduction, 2-22 segmentation, 3-30 See also: 64-bit mode, compatibility mode IA32_MISC_ENABLE MSR, 8-14 ID (identification) flag, EFLAGS register, 3-23 IDIV instruction, 7-12 IDTR register, 3-5, 3-6 IE (invalid operation exception) flag MXCSR register, 11-20 x87 FPU status word, 8-7, 8-37, 8-38 IEEE Standard 754, 4-5, 4-13, 8-1 IF (interrupt enable) flag EFLAGS register, 3-23, 6-14, 13-5, A-1 IM (invalid operation exception) mask bit MXCSR register, 11-20 x87 FPU control word, 8-11 Immediate operands, 3-26 IMUL instruction, 7-12 IN instruction, 5-8, 7-27, 13-4 INC instruction, 7-11 Indefinite description of, 4-22 floating-point format, 4-7, 4-17 integer, 4-5, 8-20 packed BCD integer, 4-13 QNaN floating-point, 4-20, 4-22 Index (operand addressing), 3-30, 3-32 Inexact result (precision) exception (#P), overview, 4-29 exception (#P), SSE-SSE2 extensions, 11-23 exception (#P), x87 FPU, 8-42 on floating-point operations, 4-23 G GDTR register, 3-5, 3-6 General purpose registers 64-bit mode, 3-6, 3-17 description of, 3-13, 3-14 overview of, 3-3, 3-6 parameter passing, 6-7 part of basic programming environment, 7-1, 7-2 using REX prefix, 3-17 General-purpose instructions 64-bit mode, 7-2 basic programming environment, 7-1 INDEX-6 Vol. 1 INDEX Infinity control flag, x87 FPU control word, 8-12 Infinity, floating-point format, 4-6, 4-19 INIT pin, 3-20 Input/output (see I/O) INS instruction, 5-8, 7-27, 13-4 Instruction operands, 1-6 Instruction pointer 64-bit mode, 7-2 EIP register, 3-14, 3-24 RIP register, 3-24 RIP, EIP, IP compared, 3-12 x87 FPU, 8-13 Instruction prefixes effect on SSE and SSE2 instructions, 11-37 REX prefix, 3-2, 3-16 Instruction set binary arithmetic instructions, 7-10 bit scan instructions, 7-19 bit test and modify instructions, 7-19 byte-set-on-condition instructions, 7-19 cacheability control instructions, 5-20, 5-25 comparison and sign change instruction, 7-11 control transfer instructions, 7-20 data movement instructions, 7-3 decimal arithmetic...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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