ia-32_volume1_basic-arch

11 18 on eflags register status flags 7 22 8 9 on x87

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Unformatted text preview: OMI instruction, 8-10, 8-26 FCOMIP instruction, 8-10, 8-26 FCOMP instruction, 8-9, 8-26 FCOMPP instruction, 8-9, 8-26 FCOS instruction, 8-7, 8-29 FDIV instruction, 8-25 FDIVP instruction, 8-25 FDIVR instruction, 8-25 FDIVRP instruction, 8-25 Feature determination, of processor, 14-1 FIADD instruction, 8-25 FICOM instruction, 8-9, 8-26 FICOMP instruction, 8-9, 8-26 FIDIV instruction, 8-25 FIDIVR instruction, 8-25 FILD instruction, 8-23 FIMUL instruction, 8-25 FINIT/FNINIT instructions, 8-7, 8-11, 8-12, 8-32 FIST instruction, 8-23 FISTP instruction, 8-23 FISTTP instruction, 5-26, 12-4 FISUB instruction, 8-25 FISUBR instruction, 8-25 Flags cross-reference with instructions, A-1 Flat memory model, 3-8, 3-18 FLD instruction, 8-23 FLD1 instruction, 8-24 FLDCW instruction, 8-10, 8-32 FLDENV instruction, 8-7, 8-13, 8-15, 8-33 FLDL2E instruction, 8-24 FLDL2T instruction, 8-24 FLDLG2 instruction, 8-24 FLDLN2 instruction, 8-24 FLDPI instruction, 8-24 FLDSW instruction, 8-32 FLDZ instruction, 8-24 Floating-point data types biasing constant, 4-7 denormalized finite number, 4-6 description of, 4-5 double extended precision format, 4-5, 4-6 double precision format, 4-5, 4-6 infinites, 4-6 normalized finite number, 4-6 single precision format, 4-5, 4-6 SSE extensions, 10-8 SSE2 extensions, 11-5 storing in memory, 4-8 x87 FPU, 8-18 zeros, 4-6 Floating-point exception handlers SSE and SSE2 extensions, 11-25, 11-26 typical actions, 4-31 x87 FPU, 8-45 Floating-point exceptions denormal operand exception (#D), 4-26, 8-39, 11-21, C-1 divide by zero exception (#Z), 4-27, 8-40, 11-22, C-1 exception conditions, 4-26 exception priority, 4-30 inexact result (precision) exception (#P), 4-29, 8-42, 11-22, C-1 invalid operation exception (#I), 4-26, 8-36, 11-20 invalid-operation exception (#IA), C-1 invalid-operation exception (#IS), C-1 invalid-operation exception (#I), C-1 numeric overflow exception (#O), 4-27, 8-40, 11-22, C-1 numeric underflow exception (#U), 4-28, 8-41, 11-22, C-1 summary of, 4-24, C-1 typical handler actions, 4-31 Floating-point format biased exponent, 4-16 description of, 8-18 exponent, 4-14 fraction, 4-14 indefinite, 4-7 QNaN floating-point indefinite, 4-22 real number system, 4-13 sign, 4-14 significand, 4-14 Floating-point numbers defined, 4-14 Vol. 1 INDEX-5 INDEX encoding, 4-7 Flush-to-zero FZ flag, MXCSR register, 10-7, 11-3 mode, 10-7 FMUL instruction, 8-25 FMULP instruction, 8-25 FNOP instruction, 8-32 Fopcode compatibility mode, 8-14 FPATAN instruction, 8-29 FPREM instruction, 8-7, 8-25, 8-30 FPREM1 instruction, 8-7, 8-25, 8-30 FPTAN instruction, 8-7 Fraction, floating-point number, 4-14 FRNDINT instruction, 8-25 FRSTOR instruction, 8-7, 8-13, 8-15, 8-33 FS register, 3-17, 3-19 FSAVE/FNSAVE instructions, 8-6, 8-7, 8-13, 8-15, 8-33 FSCALE instruction, 8-31 FSIN instruction, 8-7, 8-29 FSINCOS instruction, 8-7, 8-29 FSQRT instruction, 8-25 FST instruction, 8-23 FSTCW/FNSTCW instructions, 8-10, 8-32 FSTENV/FNSTENV instructions, 8-6, 8-13, 8-15, 8-3...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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