16 bit registers 64 bits 64 bits fpu registers

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Unformatted text preview: s physical memory. Instead, they access memory using one of three memory models: flat, segmented, or real address mode: Flat memory model -- Memory appears to a program as a single, continuous address space (Figure 3-3). This space is called a linear address space. Code, data, and stacks are all contained in this address space. Linear address space is byte addressable, with addresses running contiguously from 0 to 232 - 1 (if not in 64-bit mode). An address for any byte in linear address space is called a linear address. Segmented memory model -- Memory appears to a program as a group of independent address spaces called segments. Code, data, and stacks are typically contained in separate segments. To address a byte in a segment, a program issues a logical address. This consists of a segment selector and an offset (logical addresses are often referred to as far pointers). The segment selector identifies the segment to be accessed and the offset identifies a byte in the address space of the segment. Programs running on an IA-32 processor can address up to 16,383 segments of different sizes and types, and each segment can be as large as 232 bytes. Internally, all the segments that are defined for a system are mapped into the processor's linear address space. To access a memory location, the processor thus translates each logical address into a linear address. This translation is transparent to the application program. The primary reason for using segmented memory is to increase the reliability of programs and systems. For example, placing a program's stack in a separate 3-8 Vol. 1 BASIC EXECUTION ENVIRONMENT segment prevents the stack from growing into the code or data space and overwriting instructions or data, respectively. Real-address mode memory model -- This is the memory model for the Intel 8086 processor. It is supported to provide compatibility with existing programs written to run on the Intel 8086 processor. The real-address mode uses a specific implementation of segmented memory in which the linear address space for the program and the operating system/executive consists of an array of segments of up to 64 KBytes in size each. The maximum size of the linear address space in real-address mode is 220 bytes. See also: Chapter 15, "8086 Emulation," Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A. Flat Model Linear Address Linear Address Space* Segmented Model Segments Offset (effective address) Logical Address Segment Selector Real-Address Mode Model Offset Logical Address Segment Selector Linear Address Space Divided Into Equal Sized Segments Linear Address Space* * The linear address space can be paged when using the flat or segmented model. Figure 3-3. Three Memory Management Models Vol. 1 3-9 BASIC EXECUTION ENVIRONMENT 3.3.2 Paging and Virtual Memory With the flat or the segmented memory model, linear address space is mapped into the processor's physical address space either directly or through paging. When u...
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