ia-32_volume1_basic-arch

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Unformatted text preview: OAD/MOVE/DUPLICATE enhancement instructions, 12-4 MMX technology compatibility, 12-2 numeric error flag and IGNNE#, 12-15 packed addition/subtraction instructions, 12-5 programming environment, 12-1 REX prefixes, 12-1 SIMD floating-point exception cross reference, C-11 specialized 120-bit load instruction, 12-4 SSE compatibility, 12-2 SSE2 compatibility, 12-2 x87 FPU compatibility, 12-2 SSE3 instructions descriptions of, 12-3 SIMD floating-point exception cross-reference, C-11 summary of, 5-25 SSSE feature flag, CPUID instruction, 12-14 SSSE3 extensions 64-bit mode, 12-1 asymmetric processing, 12-2 checking for support, 12-14 compatibility, 12-2 compatibility mode, 12-1 data types, 12-1 DNA exceptions, 12-14 emulation, 12-15 enabling support in a system executive, 12-13 exceptions, 12-14 Vol. 1 INDEX-15 INDEX horizontal add/subtract instructions, 12-10 horizontal processing, 12-2 MMX technology compatibility, 12-2 multiply and add packed instructions, 12-12 numeric error flag and IGNNE#, 12-15 packed absolute value instructions, 12-11 packed align instruction, 12-13 packed multiply high instructions, 12-12 packed shuffle instruction, 12-12 programming environment, 12-1 SSSE2 compatibility, 12-2 x87 FPU compatibility, 12-2 SSSE3 instructions descriptions of, 12-9 summary of, 5-28 Stack 64-bit mode, 3-6, 6-5 64-bit mode behavior, 6-19 address-size attribute, 6-3 alignment, 6-3 alignment of stack pointer, 6-3 current stack, 6-2, 6-4 description of, 6-1 EIP register (return instruction pointer), 6-4 maximum size, 6-1 number allowed, 6-1 overview of, 3-5 passing parameters on, 6-7 popping values from, 6-1 procedure linking information, 6-4 pushing values on, 6-1 return instruction pointer, 6-4 SS register, 6-1 stack segment, 3-19, 6-1 stack-frame base pointer, EBP register, 6-4 switching on calls to interrupt and exception handlers, 6-15 on inter-privilege level calls, 6-11, 6-16 privilege levels, 6-10 width, 6-3 Stack, x87 FPU stack fault, 8-9 stack overflow and underflow exception (#IS), 8-7, 8-36, 8-37 Status flags EFLAGS register, 3-21, 8-9, 8-10, 8-28 STC instruction, 3-22, 7-28 STD instruction, 3-22, 7-29 STI instruction, 7-30, 13-5 Sticky bits, 8-7 STMXCSR instruction, 10-17, 11-35 STOS instruction, 3-22, 7-26 Streaming SIMD extensions 2 (see SSE2 extensions) Streaming SIMD extensions (see SSE extensions) String data type, 4-9 ST(0), top-of-stack register, 8-4 SUB instruction, 7-11 Superscalar microarchitecture P6 family microarchitecture, 2-3 P6 family processors, 2-7 Pentium 4 processor, 2-10 Pentium Pro processor, 2-3 Pentium processor, 2-2 System management mode (see SMM) T Tangent, x87 FPU operation, 8-29 Task gate, 6-17 Task register, 3-5 Task state segment (see TSS) Tasks exception handler, 6-17 interrupt handler, 6-17 Temporal data, 10-18 TEST instruction, 7-20 TF (trap) flag, EFLAGS register, 3-23, A-1 Thermal Monitor, 2-6 Tiny number, 4-18 TOP (stack TOP) field x87 FPU status word, 8-3, 9-12 TR register, 3-6 Trace cache, 2-10 Transcen...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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