ia-32_volume1_basic-arch

3 13 3 17 x87 fpu registers 8 1 xmm registers 3 3 10

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Unformatted text preview: instructions, 11-12 data movement instructions, 11-8 data types, 11-4, 11-5, 12-2 denormal operand exception (#D), 11-21 denormals-are-zero mode, 11-5 divide by zero exception (#Z), 11-22 exceptions, 11-18 INDEX-14 Vol. 1 INDEX floating-point format, 4-13, 4-14 generating SIMD floating-point exceptions, 11-23 guidelines for using, 11-27 handling combinations of masked and unmasked exceptions, 11-26 handling masked exceptions, 11-23 handling SIMD floating-point exceptions in software, 11-26 handling unmasked exceptions, 11-25, 11-26 inexact result exception (#P), 11-23 initialization of, 11-29 instruction prefixes, effect on SSE and SSE2 instructions, 11-37 instruction set, 5-21 instructions, 11-6, 12-3, 12-10 interaction of SIMD and x87 FPU floating-point exceptions, 11-26 interaction of SSE and SSE2 instructions with x87 FPU and MMX instructions, 11-31 interfacing with SSE and SSE2 procedures and functions, 11-34 intermixing packed and scalar floating-point and 128-bit SIMD integer instructions and data, 11-32 invalid operation exception (#I), 11-20 logical instructions, 11-9 masked responses to invalid arithmetic operations, 11-20 memory ordering instructions, 11-17 MMX technology compatibility, 11-4 numeric overflow exception (#O), 11-22 numeric underflow exception (#U), 11-22 overview of, 11-1 packed 128-Bit SIMD data types, 4-11 packed and scalar floating-point instructions, 11-6 programming environment, 11-3 QNaN floating-point indefinite, 4-22 restoring SSE and SSE2 state, 11-30 REX prefixes, 11-4 saving SSE and SSE2 state, 11-30 saving XMM register state on a procedure or function call, 11-34 shuffle instructions, 11-10 SIMD floating-point exception conditions, 11-19 SIMD floating-point exception cross reference, C-7 SIMD floating-point exception (#XF), 11-25, 11-26 SIMD floating-point exceptions, 11-19 SSE and SSE2 conversion instruction chart, 11-13 SSE compatibility, 11-4 SSE2 feature flag, CPUID instruction, 11-28 unpack instructions, 11-10 updating MMX technology routines using 128-bit SIMD integer instructions, 11-35 writing applications with, 11-27 x87 FPU compatibility, 11-4 SSE2 feature flag, CPUID instruction, 11-28, 12-7 SSE2 instructions descriptions of, 11-6, 12-3, 12-10 SIMD floating-point exception cross-reference, C-7 summary of, 5-21 SSE3 extensions 64-bit mode, 12-1 asymmetric processing, 12-2 compatibility mode, 12-1 DNA exceptions, 12-14 emulation, 12-15 enabling support in a system executive, 12-7 example verifying SS3 support, 12-8, 12-14 exceptions, 12-14 guideline for packed addition/subtraction instructions, 12-9 horizontal addition/subtraction instructions, 12-5 horizontal processing, 12-2 instruction that addresses cache line splits, 5-26 instruction that improves X87-FP integer conversion, 5-26 instructions for horizontal addition/subtraction, 5-26 instructions for packed addition/subtraction, 5-26 instructions that enhance LOAD/MOVE/DUPLICATE, 5-27 instructions that improve synchronization between agents, 5-27 L...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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