ia-32_volume1_basic-arch

3 instruction set reference a m of the intel 64 and

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Unformatted text preview: MOVNBE CMOVAE/CMOVNB CMOVNC CMOVB/CMOVNAE CMOVC CMOVBE/CMOVNA CMOVE/CMOVZ CMOVNE/CMOVNZ CMOVP/CMOVPE CMOVNP/CMOVPO (CF or ZF) = 0 CF = 0 CF = 0 CF = 1 CF = 1 (CF or ZF) = 1 ZF = 1 ZF = 0 PF = 1 PF = 0 Above/not below or equal Above or equal/not below Not carry Below/not above or equal Carry Below or equal/not above Equal/zero Not equal/not zero Parity/parity even Not parity/parity odd Status Flag States Condition Description Vol. 1 7-5 PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS Table 7-2. Conditional Move Instructions (Contd.) Instruction Mnemonic Signed Conditional Moves CMOVGE/CMOVNL CMOVL/CMOVNGE CMOVLE/CMOVNG CMOVO CMOVNO CMOVS CMOVNS (SF xor OF) = 0 (SF xor OF) = 1 ((SF xor OF) or ZF) = 1 OF = 1 OF = 0 SF = 1 SF = 0 Greater or equal/not less Less/not greater or equal Less or equal/not greater Overflow Not overflow Sign (negative) Not sign (non-negative) Status Flag States Condition Description The XADD (exchange and add) instruction swaps two operands and then stores the sum of the two operands in the destination operand. The status flags in the EFLAGS register indicate the result of the addition. This instruction can be combined with the LOCK prefix (see "LOCK--Assert LOCK# Signal Prefix" in Chapter 3, "Instruction Set Reference, A-M," of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2A) in a multiprocessing system to allow multiple processors to execute one DO loop. The CMPXCHG (compare and exchange) and CMPXCHG8B (compare and exchange 8 bytes) instructions are used to synchronize operations in systems that use multiple processors. The CMPXCHG instruction requires three operands: a source operand in a register, another source operand in the EAX register, and a destination operand. If the values contained in the destination operand and the EAX register are equal, the destination operand is replaced with the value of the other source operand (the value not in the EAX register). Otherwise, the original value of the destination operand is loaded in the EAX register. The status flags in the EFLAGS register reflect the result that would have been obtained by subtracting the destination operand from the value in the EAX register. The CMPXCHG instruction is commonly used for testing and modifying semaphores. It checks to see if a semaphore is free. If the semaphore is free, it is marked allocated; otherwise it gets the ID of the current owner. This is all done in one uninterruptible operation. In a single-processor system, the CMPXCHG instruction eliminates the need to switch to protection level 0 (to disable interrupts) before executing multiple instructions to test and modify a semaphore. For multiple processor systems, CMPXCHG can be combined with the LOCK prefix to perform the compare and exchange operation atomically. (See "Locked Atomic Operations" in Chapter 7, "Multiple-Processor Management," of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A,...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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