ia-32_volume1_basic-arch

5 27 12 4 movsldup instruction 5 27 12 4 movss

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Unformatted text preview: DQ instruction, 11-16 PUNPCKLWD instruction, 9-9 PUSH instruction, 6-1, 6-3, 7-7, 7-30 PUSHA instruction, 6-8, 7-7 PUSHF instruction, 3-20, 6-8, 7-29 PUSHFD instruction, 3-20, 6-8, 7-29 PXOR instruction, 9-10 Q QNaN floating-point indefinite, 4-6, 4-20, 4-22, 8-20 QNaNs description of, 4-20 effect on COMISD and UCOMISD, 11-10 encodings, 4-6 operating on, 4-20 rules for generating, 4-21 using in applications, 4-21 Quadword, 4-1, 9-3 Quiet NaN (see QNaN) R R8D-R15D registers, 3-16 R8-R15 registers, 3-16 RAX register, 3-16 RBP register, 3-16, 6-5 RBX register, 3-16 RC (rounding control) field MXCSR register, 4-23, 10-6 x87 FPU control word, 4-23, 8-12 RCL instruction, 7-18 RCPPS instruction, 10-12 RCPSS instruction, 10-12 RCR instruction, 7-18 RCX register, 3-16 RDI register, 3-16 RDX register, 3-16 Real address mode handling exceptions in, 6-17 handling interrupts in, 6-17 memory model, 3-9, 3-10 memory model used, 3-11 not in 64-bit mode, 3-11 overview, 3-1 Real numbers continuum, 4-14 encoding, 4-17 notation, 4-16 system, 4-13 Register operands 64-bit mode, 3-28 legacy modes, 3-27 Register stack, x87 FPU, 8-2 Registers 64-bit mode, 3-16, 3-20 control registers, 3-5 CR in 64-bit mode, 3-6 debug registers, 3-5 EFLAGS register, 3-14, 3-20 EIP register, 3-14, 3-24 general purpose registers, 3-13, 3-14 instruction pointer, 3-14 machine check registers, 3-5 memory management registers, 3-5 MMX registers, 3-3, 9-3 MSRs, 3-5 MTRRs, 3-5 MXCSR register, 10-6 performance monitoring counters, 3-5 REX prefix, 3-16 segment registers, 3-13, 3-17 x87 FPU registers, 8-1 XMM registers, 3-3, 10-4 Related literature, 1-9 REP/REPE/REPZ/REPNE/REPNZ prefixes, 7-26, 13-4 Reserved bits, 1-5 RESET pin, 3-20 RET instruction, 3-24, 6-4, 6-5, 7-21, 7-31 Return instruction pointer, 6-4 Returns, from procedure calls exception handler, return from, 6-14 far return, 6-6 inter-privilege level return, 6-10 interrupt handler, return from, 6-14 near return, 6-5 REX prefixes, 3-2, 3-16, 3-25 RF (resume) flag, EFLAGS register, 3-23, A-1 RFLAGS, 3-24 RFLAGS register, 7-30 See EFLAGS register RIP register, 6-5 64-bit mode, 7-2 description of, 3-24 relation to EIP, 7-2 ROL instruction, 7-18 ROR instruction, 7-18 Rounding modes, floating-point operations, 4-23 modes, x87 FPU, 8-12 toward zero (truncation), 4-24 INDEX-12 Vol. 1 INDEX Rounding control (RC) field MXCSR register, 4-23, 10-6 x87 FPU control word, 4-23, 8-12 RSI register, 3-16 RSP register, 3-16, 6-5 RSQRTPS instruction, 10-12 RSQRTSS instruction, 10-12 S SAHF instruction, 3-20, 7-29 SAL instruction, 7-14 SAR instruction, 7-15 Saturation arithmetic (MMX instructions), 9-5 SBB instruction, 7-11 Scalar operations defined, 10-10, 11-7 scalar double-precision FP operands, 11-7 scalar single-precision FP operands, 10-10 Scale (operand addressing), 3-30, 3-32 Scale, x87 FPU operation, 8-31 Scaling bias value, 8-41, 8-42 SCAS instruction, 3-22, 7-26 Segment defined, 3-8 maximum number, 3-8 Segment override prefixes, 3-29 Segment registers...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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