ia-32_volume1_basic-arch

5 30 12 13 pand instruction 9 10 pandn instruction 9

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Unformatted text preview: 64-bit mode, 3-20, 3-30, 7-2 default usage rules, 3-29 description of, 3-13, 3-17 part of basic programming environment, 7-1 Segment selector description of, 3-8, 3-17 segment override prefixes, 3-29 specifying, 3-29 Segmented memory model, 1-6, 3-8, 3-18 Serialization of I/O instructions, 13-7 Serializing instructions, 13-7 SETcc instructions, 3-22, 7-19 SF (sign) flag, EFLAGS register, 3-21, A-1 SF (stack fault) flag, x87 FPU status word, 8-9, 8-37 SFENCE instruction, 10-20, 11-17, 11-37 SHL instruction, 7-14 SHLD instruction, 7-17 SHR instruction, 7-15 SHRD instruction, 7-17 Shuffle instructions SSE extensions, 10-14 SSE2 extensions, 11-10 SHUFPD instruction, 11-10 SI register, 3-16 Signaling NaN (see SNaN) Signed infinity, 4-19 integers, description of, 4-4 integers, encodings, 4-5 zero, 4-18 Significand, of floating-point number, 4-14 Sign, floating-point number, 4-14 SIMD floating-point exception (#XF), 11-25 SIMD floating-point exceptions denormal operand exception (#D), 11-21 divide-by-zero (#Z), 11-22 exception conditions, 11-19 exception handlers, E-1 inexact result exception (#P), 11-23 invalid operation exception (#I), 11-20 list of, 11-19 numeric overflow exception (#O), 11-22 numeric underflow exception (#U), 11-22 precision exception (#P), 11-23 software handling, 11-26 summary of, C-1 writing exception handlers for, E-1 SIMD floating-point flag bits, 10-6 SIMD floating-point mask bits, 10-6 SIMD floating-point rounding control field, 10-6 SIMD (single-instruction, multiple-data) execution model, 2-3, 2-4, 9-4 instructions, 2-15, 5-21, 10-10 MMX instructions, 5-14 operations, on packed double-precision floating-point operands, 11-6 operations, on packed single-precision floating-point operands, 10-9 packed data types, 4-10 SSE instructions, 5-16 SSE2 instructions, 11-6, 12-3, 12-10 Sine, x87 FPU operation, 8-29 Single-precision floating-point format, 4-5 Sleep, 2-6 Smart cache, 2-6 Smart memory access, 2-13 smart memory access, 2-6 SMM memory model used, 3-11 overview, 3-1 SNaNs description of, 4-20 effect on COMISD and UCOMISD, 11-10 encodings, 4-6 operating on, 4-20 typical uses of, 4-20 using in applications, 4-21 Software compatibility, 1-5 SP register, 3-16 Speculative execution, 2-7, 2-10 Spin-wait loops programming with PAUSE instruction, 11-18 SQRTPD instruction, 11-9 SQRTPS instruction, 10-12 SQRTSD instruction, 11-9 SQRTSS instruction, 10-12 SS register, 3-17, 3-19, 6-1 SSE extensions Vol. 1 INDEX-13 INDEX 128-bit packed single-precision data type, 10-8 64-bit mode, 10-4 64-bit SIMD integer instructions, 10-16 branching on arithmetic operations, 11-36 cacheability control instructions, 10-18 cacheability hint instructions, 11-36 caller-save requirement for procedure and function calls, 11-35 checking for SSE and SSE2 support, 11-28 comparison instructions, 10-13 compatibility mode, 10-4 compatibility of SIMD and x87 FPU floating-point data types, 11-32 conversion instructions, 10-15 data movement instructions, 10-10 data t...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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