ia-32_volume1_basic-arch

7 11 indefinite description of 4 22 floating point

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Unformatted text preview: on handling in MMX code, 9-14 IA-32e mode, 9-2 instruction set, 5-14, 9-6 interfacing with MMX code, 9-13 introduction to, 9-1 memory data formats, 9-4 mixing MMX and floating-point instructions, 9-13 MMX registers, 9-3 programming environment (overview), 9-2 register mapping, 9-14 saturation arithmetic, 9-5 SIMD execution environment, 9-4 transitions between x87 FPU - MMX code, 9-12 updating MMX technology routines using 128-bit SIMD integer instructions, 11-35 using MMX code in a multitasking operating system environment, 9-14 using the EMMS instruction, 9-12 wraparound mode, 9-5 Modes of operation 64-bit mode, 3-2 compatibility mode, 3-2 memory models used with, 3-10 overview, 3-1, 3-6 protected mode, 3-1 real address mode, 3-1 system management mode (SMM), 3-1 MONITOR instruction, 5-27, 12-7 Moore's law, 2-23 MOV instruction, 7-3, 7-30 MOVAPD instruction, 11-8, 11-34 MOVAPS instruction, 10-11, 11-34 MOVD instruction, 9-8 MOVDDUP instruction, 5-27, 12-5 MOVDQ2Q instruction, 11-16 MOVDQA instruction, 11-15, 11-34 MOVDQU instruction, 11-15, 11-34 MOVHLPS instruction, 10-11 MOVHPD instruction, 11-8 MOVHPS instruction, 10-11 MOVLHPS instruction, 10-11 MOVLPD instruction, 11-8 MOVLPS instruction, 10-11 MOVMSKPD instruction, 11-8 MOVMSKPS instruction, 10-11 MOVNTDQ instruction, 11-17, 11-36 MOVNTI instruction, 11-17, 11-36 MOVNTPD instruction, 11-17, 11-36 MOVNTPS instruction, 10-18, 11-36 MOVNTQ instruction, 10-18, 11-36 MOVQ instruction, 9-8 MOVQ2DQ instruction, 11-16 MOVS instruction, 3-22, 7-26 MOVSD instruction, 11-8, 11-34 MOVSHDUP instruction, 5-27, 12-4 MOVSLDUP instruction, 5-27, 12-4 MOVSS instruction, 10-11, 11-34 MOVSX instruction, 7-10 MOVSXD instruction, 7-10 MOVUPD instruction, 11-8, 11-34 MOVUPS instruction, 10-9, 10-11, 11-34 MOVZX instruction, 7-10 MS-DOS compatibility mode, 8-45, D-1 MSRs, 3-5 MTRRs, 3-5 MUL instruction, 7-12 MULPD instruction, 11-9 MULPS instruction, 10-12 MULSD instruction, 11-9 MULSS instruction, 10-12 Multi-core technology, 2-19 Multi-threading capability, 2-19 MWAIT instruction, 5-27, 12-7 MXCSR register, 11-23 denormals-are-zero (DAZ) flag, 10-7, 11-3, 11-5 description, 10-5 flush-to-zero flag (FZ), 10-7 FXSAVE and FXRSTOR instructions, 11-34 LDMXCSR instruction, 11-35 load and store instructions, 10-17 RC field, 4-23 saving on a procedure or function call, 11-34 SIMD floating-point mask and flag bits, 10-6 SIMD floating-point rounding control field, 10-6 state management instructions, 5-20, 10-17 STMXCSR instruction, 11-35 writing to while preventing general-protection exceptions (#GP), 11-30 N NaNs description of, 4-17, 4-19 encoding of, 4-6, 4-7, 4-17 SNaNs vs. QNaNs, 4-19 Near call description of, 6-5 Vol. 1 INDEX-9 INDEX operation, 6-5 Near pointer 64-bit mode, 4-8 legacy modes, 4-8 Near return operation, 6-5 NEG instruction, 7-11 NetBurst microarchitecture (see Intel NetBurst microarchitecture) Non-arithmetic instructions, x87 FPU, 8-35 Non-number encodings, floating-point format, 4-17 Non-temporal data ca...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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