ia-32_volume1_basic-arch

7 4 eip register description of 3 24 overview 3 14

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Unformatted text preview: instructions, 7-12 EFLAGS cross-reference, A-1 EFLAGS instructions, 7-28 exchange instructions, 7-5 FXSAVE and FXRSTOR instructions, 5-13 general-purpose instructions, 5-2 grouped by processor, 5-1 increment and decrement instructions, 7-11 instruction ordering instructions, 5-20, 5-25 I/O instructions, 5-8, 7-27 logical instructions, 7-14 MMX instructions, 5-14, 9-6 multiply and divide instructions, 7-12 processor identification instruction, 7-32 repeating string operations, 7-26 rotate instructions, 7-17 segment register instructions, 7-30 shift instructions, 7-14 SIMD instructions, introduction to, 2-15 software interrupt instructions, 7-24 SSE instructions, 5-16 SSE2 instructions, 5-21 stack manipulation instructions, 7-7 string operation instructions, 7-25 summary, 5-1 system instructions, 5-30 test instruction, 7-20 type conversion instructions, 7-9 x87 FPU and SIMD state management instructions, 5-13 x87 FPU instructions, 5-10 INT instruction, 6-18, 7-31 Integers description of, 4-4 indefinite, 4-5, 8-20 signed integer encodings, 4-5 signed, description of, 4-4 unsigned integer encodings, 4-4 unsigned, description of, 4-4 Intel 64 architecture 64-bit mode, 3-2 64-bit mode instructions, 5-31 address space, 3-8 compatibility mode, 3-2 data types, 4-1 definition of, 1-2 executing calls, 6-1 general purpose instructions, 7-1 generations, 2-22 history of, 2-1 IA32e mode, 3-2 introduction, 2-22 memory organization, 3-8, 3-10 relation to IA-32, 1-2 See also: IA-32e mode Intel Advanced Digital Media Boost, 2-6, 2-13 Intel Advanced Smart Cache, 2-13 Intel Advanced Thermal Manager, 2-6 Intel Core 2 Extreme processor family, 2-6, 2-21 Intel Core Duo processor, 2-6, 2-20 Intel Core microarchitecture, 2-6, 2-13, 2-21 Intel Core Solo processor, 2-6 Intel developer link, 1-10 Intel Dynamic Power Coordination, 2-6 Intel NetBurst microarchitecture, 1-2 description of, 2-9 introduction, 2-9 Intel Pentium D processor, 2-20 Intel Pentium processor Extreme Edition, 2-19 Intel Smart Cache, 2-6 Intel Smart Memory Access, 2-6, 2-13 Intel software network link, 1-9 Intel VTune Performance Analyzer related information, 1-9 Intel Wide Dynamic Execution, 2-6, 2-13 Intel Xeon processor, 1-1 description of, 2-4 Intel Xeon processor 5100 series, 2-6, 2-21 Intel386 processor, 2-2 Intel486 processor history of, 2-2 Inter-privilege level call description of, 6-8 operation, 6-10 Inter-privilege level return description of, 6-8 operation, 6-10 Interrupt gate, 6-14 Interrupt handler, 6-13 Interrupt vector, 6-13 Interrupts 64-bit mode, 6-19 Vol. 1 INDEX-7 INDEX description of, 6-13 handler, 6-13 implicit call to an interrupt handler procedure, 6-14 implicit call to an interrupt handler task, 6-17 implicit call to interrupt handler procedure, 6-14 implicit call to interrupt handler task, 6-17 in real-address mode, 6-17 maskable, 6-13 user-defined, 6-13 vector, 6-13 INTn instruction, 7-25 INTO instruction, 6-18, 7-25, 7-31 Invalid arithmetic operand exception (#IA) description of, 8-38...
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