ia-32_volume1_basic-arch

8 programming with the x87 fpu describes the x87

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Unformatted text preview: Programming with Streaming SIMD Extensions (SSE). Describes SSE extensions, including XMM registers, the MXCSR register, and packed single-precision floating-point data types; provides an overview of the SSE instruction set and gives guidelines for writing code that accesses the SSE extensions. Chapter 11 -- Programming with Streaming SIMD Extensions 2 (SSE2). Describes SSE2 extensions, including XMM registers and packed double-precision floating-point data types; provides an overview of the SSE2 instruction set and gives guidelines for writing code that accesses SSE2 extensions. This chapter also describes SIMD floating-point exceptions that can be generated with SSE and SSE2 instructions. It also provides general guidelines for incorporating support for SSE and SSE2 extensions into operating system and applications code. Chapter 12 -- Programming with SSE3 and Supplemental SSE3. Describes SSE3 extensions; provides an overview of the SSE3 instruction set, Supplemental SSE3 and guidelines for writing code that accesses these extensions. Chapter 13 -- Input/Output. Describes the processor's I/O mechanism, including I/O port addressing, I/O instructions, and I/O protection mechanisms. Vol. 1 1-3 ABOUT THIS MANUAL Chapter 14 -- Processor Identification and Feature Determination. Describes how to determine the CPU type and features available in the processor. Appendix A -- EFLAGS Cross-Reference. Summarizes how the IA-32 instructions affect the flags in the EFLAGS register. Appendix B -- EFLAGS Condition Codes. Summarizes how conditional jump, move, and `byte set on condition code' instructions use condition code flags (OF, CF, ZF, SF, and PF) in the EFLAGS register. Appendix C -- Floating-Point Exceptions Summary. Summarizes exceptions raised by the x87 FPU floating-point and SSE/SSE2/SSE3 floating-point instructions. Appendix D -- Guidelines for Writing x87 FPU Exception Handlers. Describes how to design and write MS-DOS* compatible exception handling facilities for FPU exceptions (includes software and hardware requirements and assembly-language code examples). This appendix also describes general techniques for writing robust FPU exception handlers. Appendix E -- Guidelines for Writing SIMD Floating-Point Exception Handlers. Gives guidelines for writing exception handlers for exceptions generated by SSE/SSE2/SSE3 floating-point instructions. 1.3 NOTATIONAL CONVENTIONS This manual uses specific notation for data-structure formats, for symbolic representation of instructions, and for hexadecimal and binary numbers. This notation is described below. 1.3.1 Bit and Byte Order In illustrations of data structures in memory, smaller addresses appear toward the bottom of the figure; addresses increase toward the top. Bit positions are numbered from right to left. The numerical value of a set bit is equal to two raised to the power of the bit position. Intel 64 and IA-32 processors are "little endian" machines; this means the bytes of a word are num...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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