ia-32_volume1_basic-arch

9 2 movs instruction 7 27 movsxd instruction 7 10

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Unformatted text preview: 7-11 Decimal integers, x87 FPU, 4-13 Deeper sleep, 2-6 Denormal number (see Denormalized finite number) Denormal operand exception (#D) overview of, 4-26 SSE and SSE2 extensions, 11-21 x87 FPU, 8-38 Denormalization process, 4-19 Denormalized finite number, 4-6, 4-18 Denormals-are-zero DAZ flag, MXCSR register, 10-7, 11-3, 11-5, 11-28 mode, 10-7, 11-28 DF (direction) flag, EFLAGS register, 3-22, A-1 DH register, 3-16 DI register, 3-16 Digital media boost, 2-6 Displacement (operand addressing), 3-30, 3-31, 3-32 DIV instruction, 7-12 Divide, 4-27 Divide by zero exception (#Z) SSE and SSE2 extensions, 11-22 x87 FPU, 8-40 DIVPD instruction, 11-9 DIVPS instruction, 10-12 DIVSD instruction, 11-9 DIVSS instruction, 10-12 DL register, 3-16 DM (denormal operand exception) mask bit MXCSR register, 11-21 x87 FPU, 8-39 x87 FPU control word, 8-11 Double-extended-precision FP format, 4-5 Double-precision floating-point format, 4-5 Doubleword, 4-1 DS register, 3-17, 3-19 Dual-core technology introduction, 2-19 DX register, 3-16 Dynamic data flow analysis, 2-8 Dynamic execution, 2-8, 2-13 E EAX register, 3-14, 3-16 EBP register, 3-14, 3-16, 6-4, 6-8 EBX register, 3-14, 3-16 ECX register, 3-14, 3-16 EDI register, 3-14, 3-16 EDX register, 3-14, 3-16 Effective address, 3-30 EFLAGS register 64-bit mode, 7-2 condition codes, B-1 cross-reference with instructions, A-1 description of, 3-20 instructions that operate on, 7-28 overview, 3-14 part of basic programming environment, 7-1 restoring from stack, 6-8 saving on a procedure call, 6-8 status flags, 8-9, 8-10, 8-28 use with CMOVcc instructions, 7-4 EIP register description of, 3-24 overview, 3-14 part of basic programming environment, 7-1 relationship to CS register, 3-19 EMMS instruction, 9-10, 9-12 Enhanced Intel Deeper Sleep, 2-6 ENTER instruction, 6-19, 6-20, 7-28 ES register, 3-17, 3-19 ES (exception summary) flag x87 FPU status word, 8-44 ESC instructions, x87 FPU, 8-22 ESI register, 3-14, 3-16 ESP register, 3-16 ESP register (stack pointer), 3-14, 6-3, 6-4 Exception flags, x87 FPU status word, 8-7 Exception handlers overview of, 6-13 SIMD floating-point exceptions, E-1 SSE and SSE2 extensions, 11-25, 11-26 typical actions of a FP exception handler, 4-31 x87 FPU, 8-45 Exception priority, floating-point exceptions, 4-30 Exception-flag masks, x87 FPU control word, 8-11 Exceptions 64-bit mode, 6-19 INDEX-4 Vol. 1 INDEX description of, 6-13 handler, 6-13 implicit call to handler, 6-1 in real-address mode, 6-17 notation, 1-9 vector, 6-13 Exponent, floating-point number, 4-14 F F2XM1 instruction, 8-31 FABS instruction, 8-25 FADD instruction, 8-25 FADDP instruction, 8-25 Far call description of, 6-5 operation, 6-6 Far pointer 16-bit addressing, 3-11 32-bit addressing, 3-11 64-bit mode, 4-8 description of, 3-8, 4-8 legacy modes, 4-8 Far return operation, 6-6 FBLD instruction, 8-23 FBSTP instruction, 8-23 FCHS instruction, 8-25 FCLEX/FNCLEX instructions, 8-7 FCMOVcc instructions, 8-10, 8-23 FCOM instruction, 8-9, 8-26 FC...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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