ia-32_volume1_basic-arch

Cmpsdunord source operands nan op opd2 any opd2

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Unformatted text preview: nstruction SQRTPS SQRTPD SQRTSS SQRTSD MAXPS MAXSS MAXPD MAXSD MINPS MINSS MINPD MINSD CMPPS.LT CMPPS.LE CMPPS.NLT CMPPS.NLE CMPSS.LT CMPSS.LE CMPSS.NLT CMPSS.NLE CMPPD.LT CMPPD.LE CMPPD.NLT CMPPD.NLE CMPSD.LT CMPSD.LE CMPSD.NLT CMPSD.NLE COMISS COMISD UCOMISS UCOMISD Condition src = SNaN src < 0 (note that -0 < 0 is false) src1 = NaN or src2 = NaN Masked Response Refer to Table E-10 for NaN operands, #IA = 1 res = QNaN Indefinite, #IA = 1 res = src2, #IA = 1 src1, src2 unchanged; #IA = 1 src1, src2 unchanged; #IA = 1 src1, src2 unchanged; #IA = 1 src1 = NaN or src2 = NaN res = src2, #IA = 1 src1 = NaN or src2 = NaN Refer to Table E-4 and Table E-5 for NaN operands; #IA = 1 src1 = NaN or src2 = NaN Refer to Table E-6 for NaN operands Refer to Table E-7 for NaN operands src1, src2, EFLAGS unchanged; #IA = 1 src1, src2, EFLAGS unchanged; #IA = 1 src1 = SNaN or src2 = SNaN E-14 Vol. 1 GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS Table E-13. #I - Invalid Operations (Contd.) Unmasked Response and Exception Code src unchanged, #IA = 1 Instruction CVTPS2PI CVTSS2SI CVTPD2PI CVTSD2SI CVTPS2DQ CVTPD2DQ CVTTPS2PI CVTTSS2SI CVTTPD2PI CVTTSD2SI CVTTPS2DQ CVTTPD2DQ CVTPS2PD CVTSS2SD CVTPD2PS CVTSD2SS NOTES: Condition src = NaN, Inf, or |(src)rnd | > 7FFFFFFFH and (src)rnd 80000000H See Note2 for information on rnd. src = NaN, Inf, or |(src)rz | > 7FFFFFFFH and (src)rz 80000000H See Note2 for information on rz. src = NAN src = NAN Masked Response res = Integer Indefinite, #IA = 1 res = Integer Indefinite, #IA = 1 src unchanged, #IA = 1 Refer to Table E-11 for NaN operands Refer to Table E-12 for NaN operands src unchanged, #IA = 1 src unchanged, #IA = 1 1. For Tables E-13 to E-18: - src denotes the single source operand of a unary operation. - src1, src2 denote the first and second source operand of a binary operation. - res denotes the numerical result of an operation. 2. rnd signifies the user rounding mode from MXCSR, and rz signifies the rounding mode toward zero. (truncate), when rounding a floating-point value to an integer. For more information, refer to Table 4-8. 3. For NAN encodings, see Table 4-3. Table E-14. #Z - Divide-by-Zero Unmasked Response and Exception Code src1, src2 unchanged; #ZE = 1 Instruction DIVPS DIVSS DIVPD DIVPS Condition src1 = finite non-zero (normal, or denormal) src2 = 0 Masked Response res = Inf, #ZE = 1 Vol. 1 E-15 GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS Table E-15. #D - Denormal Operand Instruction ADDPS ADDPD ADDSUBPS ADDSUBPD HADDPS HADDPD SUBPS SUBPD HSUBPS HSUBPD MULPS MULPD DIVPS DIVPD SQRTPS SQRTPD MAXPS MAXPD MINPS MINPD CMPPS CMPPD ADDSS ADDSD SUBSS SUBSD MULSS MULSD DIVSS DIVSD SQRTSS SQRTSD MAXSS MAXSD MINSS MINSD CMPSS CMPSD COMISS COMISD UCOMISS UCOMISD CVTPS2PD Condition src1 = denormal1 or src2 = denormal (and the DAZ bit in MXCSR is 0) Masked Response res = Result rounded to the destination precision and using the bounded exponent, but only if no unmasked postc...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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