ia-32_volume1_basic-arch

Exceptions in software for information on handling

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Unformatted text preview: nd, with no internal sub-operand exception flags being set. Following the computations, the individual sub-operand exceptions flags for denormal operand, 11-24 Vol. 1 PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2) numeric underflow, inexact result, and numeric overflow are OR'd and the corresponding flags are set in the MXCSR register. The net result of this computation is that: Multiplication of X0 and Y0 produces a normalized finite result Multiplication of X1 and Y1 produces a normalized finite result Multiplication of X2 and Y2 produces a floating-point result Multiplication of X3 and Y3 produces a tiny, inexact, finite result Denormal operand, numeric underflow, numeric underflow, and inexact result flags are set in the MXCSR register 11.5.3.2 Handling Unmasked Exceptions If all exceptions are unmasked, the processor: 1. First detects any pre-computation exceptions: it ORs those exceptions, sets the appropriate exception flags, leaves the source and destination operands unaltered, and goes to step 2. If it does not detect any pre-computation exceptions, it goes to step 5. 2. Checks CR4.OSXMMEXCPT[bit 10]. If this flag is set, the processor goes to step 3; if the flag is clear, it generates an invalid-opcode exception (#UD) and makes an implicit call to the invalid-opcode exception handler. 3. Generates a SIMD floating-point exception (#XF) and makes an implicit call to the SIMD floating-point exception handler. 4. If the exception handler is able to fix the source operands that generated the precomputation exceptions or mask the condition in such a way as to allow the processor to continue executing the instruction, the processor resumes instruction execution as described in step 5. 5. Upon returning from the exception handler (or if no pre-computation exceptions were detected), the processor checks for post-computation exceptions. If the processor detects any post-computation exceptions: it ORs those exceptions, sets the appropriate exception flags, leaves the source and destination operands unaltered, and repeats steps 2, 3, and 4. 6. Upon returning from the exceptions handler in step 4 (or if no post-computation exceptions were detected), the processor completes the execution of the instruction. The implication of this procedure is that for unmasked exceptions, the processor can generate a SIMD floating-point exception (#XF) twice: once if it detects precomputation exception conditions and a second time if it detects post-computation exception conditions. For example, if SIMD floating-point exceptions are unmasked for the computation shown in Figure 11-9, the processor would generate one SIMD floating-point exception for denormal operand conditions and a second SIMD floating-point exception for overflow and underflow (no inexact result exception Vol. 1 11-25 PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2) would be generated because the multiplications of X0 and Y0 and of X1 and Y1 are exact). 11.5.3.3 Handling Combinations of Maske...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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