Unformatted text preview: e IA-32 architecture, and across all floating-point instructions, a floating-point exception can be initiated from any time during the excepting floating-point instruction, up to just before the next floatingpoint instruction. The "next" floating-point instruction may be the FNSAVE used to save the x87 FPU state for a task switch. In the case of "no-wait:" instructions such as FNSAVE, the interrupt from a previously excepting instruction (NE = 0 case) may arrive just before the no-wait instruction, during, or shortly thereafter with a system dependent delay. Note that this implies that an floating-point exception might be registered during the state swap process itself, and the kernel and floating-point exception interrupt handler must be prepared for this case. A simple way to handle the case of exceptions arriving during x87 FPU state swaps is to allow the kernel to be one of the x87 FPU owning threads. A reserved thread identifier is used to indicate kernel ownership of the x87 FPU. During an floating-point state swap, the "x87 FPU owner" variable should be set to indicate the kernel as the current owner. At the completion of the state swap, the variable should be set to indicate the new owning thread. The numeric exception handler needs to check the x87 FPU owner and discard any numeric exceptions that occur while the kernel is the x87 Vol. 1 D-25 GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS FPU owner. A more general flow for a DNA exception handler that handles this case is shown in Figure D-5. Numeric exceptions received while the kernel owns the x87 FPU for a state swap must be discarded in the kernel without being dispatched to a handler. A flow for a numeric exception dispatch routine is shown in Figure D-6. It may at first glance seem that there is a possibility of floating-point exceptions being lost because of exceptions that are discarded during state swaps. This is not the case, as the exception will be re-issued when the floating-point state is reloaded. Walking through state swaps both with and without pending numeric exceptions will clarify the operation of these two handlers. DNA Handler Entry <other handler set up code> Current Thread same as FPU Owner? No FPU Owner := Kernel FNSAVE to Old Thread's FP Save Area (may cause numeric exception) FRSTOR from Current Thread's FP Save Area <other handler code> FPU Owner := Current Thread Yes <handler final clean-up> CLTS (clears CR0.TS) Exit DNA Handler Figure D-5. General Program Flow for DNA Exception Handler D-26 Vol. 1 GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS Numeric Exception Entry Is Kernel FPU Owner? No Normal Dispatch to Numeric Exception Handler Yes Exit Figure D-6. Program Flow for a Numeric Exception Dispatch Routine Case #1: x87 FPU State Swap Without Numeric Exception
Assume two threads A and B, both using the floating-point unit. Let A be the thread to have most recently executed a floating-point instruction, w...
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- Winter '11
- X86, Intel corporation, 64-bit mode, fpu floating-point exception, FPU Control Instructions