Unformatted text preview: PU stores the opcode of the last non-control instruction executed in an 11-bit x87 FPU opcode register. (This information provides state information for exception handlers.) Only the first and second opcode bytes (after all prefixes) are stored in the x87 FPU opcode register. Figure 8-8 shows the encoding of these two bytes. Since the upper 5 bits of the first opcode byte are the same for all floatingpoint opcodes (11011B), only the lower 3 bits of this byte are stored in the opcode register. 18.104.22.168 Fopcode Compatibility Sub-mode Beginning with the Pentium 4 and Intel Xeon processors, the IA-32 architecture provides program control over the storing of the last instruction opcode (sometimes referred to as the fopcode). Here, bit 2 of the IA32_MISC_ENABLE MSR enables (set) or disables (clear) the fopcode compatibility mode. If FOP code compatibility mode is enabled, the FOP is defined as it has always been in previous IA32 implementations (always defined as the FOP of the last non-transparent FP instruction executed before a FSAVE/FSTENV/FXSAVE). If FOP code compatibility mode is disabled (default), FOP is only valid if the last non-transparent FP instruction executed before a FSAVE/FSTENV/FXSAVE had an unmasked exception. 8-14 Vol. 1 PROGRAMMING WITH THE X87 FPU 7 1st Instruction Byte 2 2nd Instruction Byte 0 7 0 10 8 7 0 x87 FPU Opcode Register Figure 8-8. Contents of x87 FPU Opcode Registers
The fopcode compatibility mode should be enabled only when x87 FPU floating-point exception handlers are designed to use the fopcode to analyze program performance or restart a program after an exception has been handled. 8.1.10 Saving the x87 FPU's State with FSTENV/FNSTENV and FSAVE/FNSAVE The FSTENV/FNSTENV and FSAVE/FNSAVE instructions store x87 FPU state information in memory for use by exception handlers and other system and application software. The FSTENV/FNSTENV instruction saves the contents of the status, control, tag, x87 FPU instruction pointer, x87 FPU operand pointer, and opcode registers. The FSAVE/FNSAVE instruction stores that information plus the contents of the x87 FPU data registers. Note that the FSAVE/FNSAVE instruction also initializes the x87 FPU to default values (just as the FINIT/FNINIT instruction does) after it has saved the original state of the x87 FPU. The manner in which this information is stored in memory depends on the operating mode of the processor (protected mode or real-address mode) and on the operandsize attribute in effect (32-bit or 16-bit). See Figures 8-9 through 8-12. In virtual8086 mode or SMM, the real-address mode formats shown in Figure 8-12 is used. See Chapter 24, "System Management," of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B, for information on using the x87 FPU while in SMM. The FLDENV and FRSTOR instructions allow x87 FPU state information to be loaded from memory into the x87 FPU. Here, the FLDENV instruction loads only the status, control, tag, x87 FPU ins...
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- Winter '11
- X86, Intel corporation, 64-bit mode, fpu floating-point exception, FPU Control Instructions