ia-32_volume1_basic-arch

Fpu data registers have been passed to another

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Unformatted text preview: uctions, or by overwriting the flags with an FRSTOR or FLDENV instruction. The B-bit (bit 15) is included for 8087 compatibility only. It reflects the contents of the ES flag. Vol. 1 8-7 PROGRAMMING WITH THE X87 FPU Table 8-1. Condition Code Interpretation Instruction FCOM, FCOMP, FCOMPP, FICOM, FICOMP, FTST, FUCOM, FUCOMP, FUCOMPP FCOMI, FCOMIP, FUCOMI, FUCOMIP FXAM FPREM, FPREM1 Q2 C0 C3 C2 Operands are not Comparable C1 0 or #IS Result of Comparison Undefined. (These instructions set the status flags in the EFLAGS register.) Operand class Q1 0 = reduction complete 1 = reduction incomplete #IS Sign Q0 or #IS F2XM1, FADD, FADDP, FBSTP, FCMOVcc, FIADD, FDIV, FDIVP, FDIVR, FDIVRP, FIDIV, FIDIVR, FIMUL, FIST, FISTP, FISUB, FISUBR,FMUL, FMULP, FPATAN, FRNDINT, FSCALE, FST, FSTP, FSUB, FSUBP, FSUBR, FSUBRP,FSQRT, FYL2X, FYL2XP1 FCOS, FSIN, FSINCOS, FPTAN Undefined Roundup or #IS Undefined 0 = source operand within range 1 = source operand out of range Roundup or #IS (Undefined if C2 = 1) FABS, FBLD, FCHS, FDECSTP, FILD, FINCSTP, FLD, Load Constants, FSTP (ext. prec.), FXCH, FXTRACT FLDENV, FRSTOR FFREE, FLDCW, FCLEX/FNCLEX, FNOP, FSTCW/FNSTCW, FSTENV/FNSTENV, FSTSW/FNSTSW, FINIT/FNINIT, FSAVE/FNSAVE 0 Undefined 0 or #IS Each bit loaded from memory Undefined 0 0 0 8-8 Vol. 1 PROGRAMMING WITH THE X87 FPU 8.1.3.4 Stack Fault Flag The stack fault flag (bit 6 of the x87 FPU status word) indicates that stack overflow or stack underflow has occurred with data in the x87 FPU data register stack. The x87 FPU explicitly sets the SF flag when it detects a stack overflow or underflow condition, but it does not explicitly clear the flag when it detects an invalid-arithmeticoperand condition. When this flag is set, the condition code flag C1 indicates the nature of the fault: overflow (C1 = 1) and underflow (C1 = 0). The SF flag is a "sticky" flag, meaning that after it is set, the processor does not clear it until it is explicitly instructed to do so (for example, by an FINIT/FNINIT, FCLEX/FNCLEX, or FSAVE/FNSAVE instruction). See Section 8.1.7, "x87 FPU Tag Word," for more information on x87 FPU stack faults. 8.1.4 Branching and Conditional Moves on Condition Codes The x87 FPU (beginning with the P6 family processors) supports two mechanisms for branching and performing conditional moves according to comparisons of two floating-point values. These mechanism are referred to here as the "old mechanism" and the "new mechanism." The old mechanism is available in x87 FPU's prior to the P6 family processors and in P6 family processors. This mechanism uses the floating-point compare instructions (FCOM, FCOMP, FCOMPP, FTST, FUCOMPP, FICOM, and FICOMP) to compare two floating-point values and set the condition code flags (C0 through C3) according to the results. The contents of the condition code flags are then copied into the status flags of the EFLAGS register using a two step process (see Figure 8-5): 1. The FSTSW AX instruction...
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