Floating point indefinite for the floating point data

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: when the intermediate results of the computation are subject to rounding. The round toward zero mode (sometimes called the "chop" mode) is commonly used when performing integer arithmetic with the x87 FPU. The rounded result is called the inexact result. When the processor produces an inexact result, the floating-point precision (inexact) flag (PE) is set (see Section, "Inexact-Result (Precision) Exception (#P)"). The rounding modes have no effect on comparison operations, operations that produce exact results, or operations that produce NaN results. Rounding Control (RC) Fields In the Intel 64 and IA-32 architectures, the rounding mode is controlled by a 2-bit rounding-control (RC) field (Table 4-8 shows the encoding of this field). The RC field is implemented in two different locations: x87 FPU control register (bits 10 and 11) Vol. 1 4-23 DATA TYPES The MXCSR register (bits 13 and 14) Although these two RC fields perform the same function, they control rounding for different execution environments within the processor. The RC field in the x87 FPU control register controls rounding for computations performed with the x87 FPU instructions; the RC field in the MXCSR register controls rounding for SIMD floatingpoint computations performed with the SSE/SSE2 instructions. Truncation with SSE and SSE2 Conversion Instructions The following SSE/SSE2 instructions automatically truncate the results of conversions from floating-point values to integers when the result it inexact: CVTTPD2DQ, CVTTPS2DQ, CVTTPD2PI, CVTTPS2PI, CVTTSD2SI, CVTTSS2SI. Here, truncation means the round toward zero mode described in Table 4-8. 4.9 OVERVIEW OF FLOATING-POINT EXCEPTIONS The following section provides an overview of floating-point exceptions and their handling in the IA-32 architecture. For information specific to the x87 FPU and to the SSE/SSE2/SSE3 extensions, refer to the following sections: Section 8.4, "x87 FPU Floating-Point Exception Handling" Section 11.5, "SSE, SSE2, and SSE3 Exceptions" When operating on floating-point operands, the IA-32 architecture recognizes and detects six classes of exception conditions: Invalid operation (#I) Divide-by-zero (#Z) Denormalized operand (#D) Numeric overflow (#O) Numeric underflow (#U) Inexact result (precision) (#P) The nomenclature of "#" symbol followed by one or two letters (for example, #P) is used in this manual to indicate exception conditions. It is merely a short-hand form and is not related to assembler mnemonics. NOTE All of the exceptions listed above except the denormal-operand exception (#D) are defined in IEEE Standard 754. The invalid-operation, divide-by-zero and denormal-operand exceptions are precomputation exceptions (that is, they are detected before any arithmetic operation 4-24 Vol. 1 DATA TYPES occurs). The numeric-underflow, numeric-overflow and precision exceptions are post-computation exceptions. Each of the six exception classes h...
View Full Document

{[ snackBarMessage ]}

Ask a homework question - tutors are online