Unformatted text preview: when the intermediate results of the computation are subject to rounding. The round toward zero mode (sometimes called the "chop" mode) is commonly used when performing integer arithmetic with the x87 FPU. The rounded result is called the inexact result. When the processor produces an inexact result, the floatingpoint precision (inexact) flag (PE) is set (see Section 4.9.1.6, "InexactResult (Precision) Exception (#P)"). The rounding modes have no effect on comparison operations, operations that produce exact results, or operations that produce NaN results. 4.8.4.1 Rounding Control (RC) Fields In the Intel 64 and IA32 architectures, the rounding mode is controlled by a 2bit roundingcontrol (RC) field (Table 48 shows the encoding of this field). The RC field is implemented in two different locations: x87 FPU control register (bits 10 and 11) Vol. 1 423 DATA TYPES The MXCSR register (bits 13 and 14) Although these two RC fields perform the same function, they control rounding for different execution environments within the processor. The RC field in the x87 FPU control register controls rounding for computations performed with the x87 FPU instructions; the RC field in the MXCSR register controls rounding for SIMD floatingpoint computations performed with the SSE/SSE2 instructions. 4.8.4.2 Truncation with SSE and SSE2 Conversion Instructions The following SSE/SSE2 instructions automatically truncate the results of conversions from floatingpoint values to integers when the result it inexact: CVTTPD2DQ, CVTTPS2DQ, CVTTPD2PI, CVTTPS2PI, CVTTSD2SI, CVTTSS2SI. Here, truncation means the round toward zero mode described in Table 48. 4.9 OVERVIEW OF FLOATINGPOINT EXCEPTIONS The following section provides an overview of floatingpoint exceptions and their handling in the IA32 architecture. For information specific to the x87 FPU and to the SSE/SSE2/SSE3 extensions, refer to the following sections: Section 8.4, "x87 FPU FloatingPoint Exception Handling" Section 11.5, "SSE, SSE2, and SSE3 Exceptions" When operating on floatingpoint operands, the IA32 architecture recognizes and detects six classes of exception conditions: Invalid operation (#I) Dividebyzero (#Z) Denormalized operand (#D) Numeric overflow (#O) Numeric underflow (#U) Inexact result (precision) (#P) The nomenclature of "#" symbol followed by one or two letters (for example, #P) is used in this manual to indicate exception conditions. It is merely a shorthand form and is not related to assembler mnemonics. NOTE
All of the exceptions listed above except the denormaloperand exception (#D) are defined in IEEE Standard 754. The invalidoperation, dividebyzero and denormaloperand exceptions are precomputation exceptions (that is, they are detected before any arithmetic operation 424 Vol. 1 DATA TYPES occurs). The numericunderflow, numericoverflow and precision exceptions are postcomputation exceptions. Each of the six exception classes h...
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 Winter '11
 Watlins
 X86, Intel corporation, 64bit mode, fpu floatingpoint exception, FPU Control Instructions

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