ia-32_volume1_basic-arch

Handlers a diagram of the control flow in handling an

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Unformatted text preview: op Opd2 (any Opd2) Opd1 op SNaN (any Opd1) QNaN op Opd2 (any Opd2 SNaN) Opd1 op QNaN (any Opd1 SNaN) Masked Result OF, SF, AF = 000 ZF, PF, CF = 111 OF, SF, AF = 000 ZF, PF, CF = 111 OF, SF, AF = 000 ZF, PF, CF = 111 OF, SF, AF = 000 ZF, PF, CF = 111 Unmasked Result None None OF, SF, AF = 000 ZF, PF, CF = 111 (not an exception) OF, SF, AF = 000 ZF, PF, CF = 111 (not an exception) E-10 Vol. 1 GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS Table E-8. CVTPS2PI, CVTSS2SI, CVTTPS2PI, CVTTSS2SI, CVTPD2PI, CVTSD2SI, CVTTPD2PI, CVTTSD2SI, CVTPS2DQ, CVTTPS2DQ, CVTPD2DQ, CVTTPD2DQ Source Operand SNaN Masked Result 80000000H or 80000000000000001 (Integer Indefinite) 80000000H or 80000000000000001 (Integer Indefinite) Unmasked Result None QNaN None NOTE: 1. 32-bit results are for single, and 64-bit results for double precision operations. Table E-9. MAXPS, MAXSS, MINPS, MINSS, MAXPD, MAXSD, MINPD, MINSD Source Operands Opd1 op NaN2 (any Opd1) NaN1 op Opd2 (any Opd2) Masked Result NaN2 Opd2 Unmasked Result None None NOTE: 1. SNaN and QNaN operands raise an Invalid Operation fault. Table E-10. SQRTPS, SQRTSS, SQRTPD, SQRTSD Source Operand QNaN SNaN Masked Result QNaN SNaN | 00400000H or SNaN | 0008000000000000H1 Single precision or double precision QNaN Indefinite Unmasked Result QNaN (not an exception) None Source operand is not SNaN; but #I is signaled (e.g. for sqrt (-1.0)) None NOTE: 1. SNaN | 00400000H is a quiet NaN in single precision format (if SNaN is in single precision) and SNaN | 0008000000000000H is a quiet NaN in double precision format (if SNaN is in double precision), obtained from the signaling NaN given as input. Vol. 1 E-11 GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS Table E-11. CVTPS2PD, CVTSS2SD Source Operands QNaN SNaN Masked Result QNaN1 1 Unmasked Result QNaN11 (not an exception) None QNaN12 NOTES: 1. The double precision output QNaN1 is created from the single precision input QNaN as follows: the sign bit is preserved, the 8-bit exponent FFH is replaced by the 11-bit exponent 7FFH, and the 24-bit significand is extended to a 53-bit significand by appending 29 bits equal to 0. 2. The double precision output QNaN1 is created from the single precision input SNaN as follows: the sign bit is preserved, the 8-bit exponent FFH is replaced by the 11-bit exponent 7FFH, and the 24-bit significand is extended to a 53-bit significand by pending 29 bits equal to 0. The second most significant bit of the significand is changed from 0 to 1 to convert the signaling NaN into a quiet NaN. Table E-12. CVTPD2PS, CVTSD2SS Source Operands QNaN SNaN Masked Result QNaN11 QNaN12 Unmasked Result QNaN11 (not an exception) None NOTES: 1. The single precision output QNaN1 is created from the double precision input QNaN as follows: the sign bit is preserved, the 11-bit exponent 7FFH is replaced by the 8-bit exponent FFH, and the 53-bit significand is truncated to a 24-bit significand by removing its 29 least significant bits. 2. The...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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