ia-32_volume1_basic-arch

Handlers e43 example simd floating point emulation

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Unformatted text preview: nt cw; // 16 bits // have to check first for faults (V, D, Z), and then for traps (O, U, I) // initialize x87 FPU (floating-point exceptions are masked) _asm { fninit; } result_tiny = 0; result_huge = 0; switch (exc_env->operation) { case case case case case case case case ADDPS: ADDSS: SUBPS: SUBSS: MULPS: MULSS: DIVPS: DIVSS: uiopd1 = exc_env->operand1_uint32; // copy as unsigned int // do not copy as float to avoid conversion // of SNaN to QNaN by compiled code uiopd2 = exc_env->operand2_uint32; // do not copy as float to avoid conversion of SNaN // to QNaN by compiled code uiopd1 = check_for_daz (uiopd1); // operand1 = +0.0 * operand1 if it is // denormal and DAZ=1 uiopd2 = check_for_daz (uiopd2); // operand2 = +0.0 * operand2 if it is // denormal and DAZ=1 // execute the operation and check whether the invalid, denormal, or // divide by zero flags are set and the respective exceptions enabled // set control word with rounding mode set to exc_env->rounding_mode, // single precision, and all exceptions disabled E-24 Vol. 1 GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS switch (exc_env->rounding_mode) { case ROUND_TO_NEAREST: cw = 0x003f; // round to nearest, single precision, exceptions masked break; case ROUND_DOWN: cw = 0x043f; // round down, single precision, exceptions masked break; case ROUND_UP: cw = 0x083f; // round up, single precision, exceptions masked break; case ROUND_TO_ZERO: cw = 0x0c3f; // round to zero, single precision, exceptions masked break; default: ; } __asm { fldcw WORD PTR cw; } // compute result and round to the destination precision, with // "unbounded" exponent (first IEEE rounding) switch (exc_env->operation) { case ADDPS: case ADDSS: // perform the addition __asm { fnclex; // load input operands fld DWORD PTR uiopd1; // may set denormal or invalid status flags fld DWORD PTR uiopd2; // may set denormal or invalid status flags faddp st(1), st(0); // may set inexact or invalid status flags // store result fstp QWORD PTR dbl_res24; // exact } break; case SUBPS: case SUBSS: // perform the subtraction __asm { fnclex; // load input operands fld DWORD PTR uiopd1; // may set denormal or invalid status flags fld DWORD PTR uiopd2; // may set denormal or invalid status flags fsubp st(1), st(0); // may set the inexact or invalid status flags // store result fstp QWORD PTR dbl_res24; // exact } break; Vol. 1 E-25 GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS case MULPS: case MULSS: // perform the multiplication __asm { fnclex; // load input operands fld DWORD PTR uiopd1; // may set denormal or invalid status flags fld DWORD PTR uiopd2; // may set denormal or invalid status flags fmulp st(1), st(0); // may set inexact or invalid status flags // store result fstp QWORD PTR dbl_res24; // exact } break; case DIVPS: case DIVSS: // perform the division __asm { fnclex; // load input operands fld DWORD PTR uiopd1; // may set denormal or invalid status flags fld DWORD PTR uiopd2; /...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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