ia-32_volume1_basic-arch

Ia 32 architecture in the pentium ii processor family

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Unformatted text preview: ess mode, virtual 8086 mode. The following sections in this chapter describe the programming environment for SSE2 extensions including: the 128-bit XMM floating-point register set, data types, and SSE2 instructions. It also describes exceptions that can be generated with the SSE and SSE2 instructions and gives guidelines for writing applications with SSE and SSE2 extensions. For additional information about SSE2 extensions, see: Intel 64 and IA-32 Architectures Software Developer's Manual, Volumes 2A & 2B, provide a detailed description of individual SSE3 instructions. 11-2 Vol. 1 PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2) Chapter 12, "System Programming for Streaming SIMD Instruction Sets," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, gives guidelines for integrating the SSE and SSE2 extensions into an operatingsystem environment. 11.2 SSE2 PROGRAMMING ENVIRONMENT Figure 11-1 shows the programming environment for SSE2 extensions. No new registers or other instruction execution state are defined with SSE2 extensions. SSE2 instructions use the XMM registers, the MMX registers, and/or IA-32 general-purpose registers, as follows: XMM registers -- These eight registers (see Figure 10-2) are used to operate on packed or scalar double-precision floating-point data. Scalar operations are operations performed on individual (unpacked) double-precision floating-point values stored in the low quadword of an XMM register. XMM registers are also used to perform operations on 128-bit packed integer data. They are referenced by the names XMM0 through XMM7. Address Space XMM Registers Eight 128-Bit 32 Bits 232 -1 MXCSR Register MMX Registers Eight 64-Bit General-Purpose Registers Eight 32-Bit 0 EFLAGS Register 32 Bits Figure 11-1. Steaming SIMD Extensions 2 Execution Environment MXCSR register -- This 32-bit register (see Figure 10-3) provides status and control bits used in floating-point operations. The denormals-are-zeros and flush-to-zero flags in this register provide a higher performance alternative for the handling of denormal source operands and denormal (underflow) results. For Vol. 1 11-3 PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2) more information on the functions of these flags see Section 10.2.3.4, "Denormals-Are-Zeros," and Section 10.2.3.3, "Flush-To-Zero." MMX registers -- These eight registers (see Figure 9-2) are used to perform operations on 64-bit packed integer data. They are also used to hold operands for some operations performed between MMX and XMM registers. MMX registers are referenced by the names MM0 through MM7. General-purpose registers -- The eight general-purpose registers (see Figure 3-5) are used along with the existing IA-32 addressing modes to address operands in memory. MMX and XMM registers cannot be used to address memory. The general-purpose registers are also used to hold operands for some SSE2 instructions. These registers are referenced by...
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