ia-32_volume1_basic-arch

Instead it is loaded implicitly by instructions or

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Unformatted text preview: is generally disabled, segment register loads may cause the processor to perform segment access assists. During these activities, enabled processors will still perform most of the legacy checks on loaded values (even if the checks are not applicable in 64-bit mode). Such checks are needed because a segment register loaded in 64-bit mode may be used by an application running in compatibility mode. Limit checks for CS, DS, ES, SS, FS, and GS are disabled in 64-bit mode. 3.4.3 EFLAGS Register The 32-bit EFLAGS register contains a group of status flags, a control flag, and a group of system flags. Figure 3-8 defines the flags within this register. Following initialization of the processor (either by asserting the RESET pin or the INIT pin), the state of the EFLAGS register is 00000002H. Bits 1, 3, 5, 15, and 22 through 31 of this register are reserved. Software should not use or depend on the states of any of these bits. Some of the flags in the EFLAGS register can be modified directly, using specialpurpose instructions (described in the following sections). There are no instructions that allow the whole register to be examined or modified directly. The following instructions can be used to move groups of flags to and from the procedure stack or the EAX register: LAHF, SAHF, PUSHF, PUSHFD, POPF, and POPFD. After the contents of the EFLAGS register have been transferred to the procedure stack or EAX register, the flags can be examined and modified using the processor's bit manipulation instructions (BT, BTS, BTR, and BTC). When suspending a task (using the processor's multitasking facilities), the processor automatically saves the state of the EFLAGS register in the task state segment (TSS) for the task being suspended. When binding itself to a new task, the processor loads the EFLAGS register with data from the new task's TSS. When a call is made to an interrupt or exception handler procedure, the processor automatically saves the state of the EFLAGS registers on the procedure stack. When 3-20 Vol. 1 BASIC EXECUTION ENVIRONMENT an interrupt or exception is handled with a task switch, the state of the EFLAGS register is saved in the TSS for the task being suspended. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 V V I I I A V R 0 N 0 0 0 0 0 0 0 0 0 0 T C M F D P F I O P L O D I T S Z P C A F F F F F F 0 F 0 F 1 F X X X X X X X X S C X X S S S S S ID Flag (ID) Virtual Interrupt Pending (VIP) Virtual Interrupt Flag (VIF) Alignment Check (AC) Virtual-8086 Mode (VM) Resume Flag (RF) Nested Task (NT) I/O Privilege Level (IOPL) Overflow Flag (OF) Direction Flag (DF) Interrupt Enable Flag (IF) Trap Flag (TF) Sign Flag (SF) Zero Flag (ZF) Auxiliary Carry Flag (AF) Parity Flag (PF) Carry Flag (CF) S Indicates a Status Flag C Indicates a Control Flag X Indicates a System Flag Reserved bit positions. DO NOT USE. Always set to values previously read. Figure 3-8. EFLAGS Register As the IA-32 Architecture has evolved, flags have...
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