ia-32_volume1_basic-arch

Intel 64 and ia 32 architectures software developers

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Unformatted text preview: moves the x87 FPU status word into the AX register. 2. The SAHF instruction copies the upper 8 bits of the AX register, which includes the condition code flags, into the lower 8 bits of the EFLAGS register. When the condition code flags have been loaded into the EFLAGS register, conditional jumps or conditional moves can be performed based on the new settings of the status flags in the EFLAGS register. Vol. 1 8-9 PROGRAMMING WITH THE X87 FPU 15 Condition Status Flag Code C0 C1 C2 C3 CF (none) PF ZF C 3 x87 FPU Status Word C C C 2 1 0 0 FSTSW AX Instruction 15 C 3 AX Register C C C 2 1 0 0 SAHF Instruction 31 EFLAGS Register 7 Z F 0 P C F 1 F Figure 8-5. Moving the Condition Codes to the EFLAGS Register The new mechanism is available beginning with the P6 family processors. Using this mechanism, the new floating-point compare and set EFLAGS instructions (FCOMI, FCOMIP, FUCOMI, and FUCOMIP) compare two floating-point values and set the ZF, PF, and CF flags in the EFLAGS register directly. A single instruction thus replaces the three instructions required by the old mechanism. Note also that the FCMOVcc instructions (also new in the P6 family processors) allow conditional moves of floating-point values (values in the x87 FPU data registers) based on the setting of the status flags (ZF, PF, and CF) in the EFLAGS register. These instructions eliminate the need for an IF statement to perform conditional moves of floating-point values. 8.1.5 x87 FPU Control Word The 16-bit x87 FPU control word (see Figure 8-6) controls the precision of the x87 FPU and rounding method used. It also contains the x87 FPU floating-point exception mask bits. The control word is cached in the x87 FPU control register. The contents of this register can be loaded with the FLDCW instruction and stored in memory with the FSTCW/FNSTCW instructions. 8-10 Vol. 1 PROGRAMMING WITH THE X87 FPU Infinity Control Rounding Control Precision Control 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X RC PC P U O Z D I M M M M M M Exception Masks Precision Underflow Overflow Zero Divide Denormal Operand Invalid Operation Reserved Figure 8-6. x87 FPU Control Word When the x87 FPU is initialized with either an FINIT/FNINIT or FSAVE/FNSAVE instruction, the x87 FPU control word is set to 037FH, which masks all floating-point exceptions, sets rounding to nearest, and sets the x87 FPU precision to 64 bits. 8.1.5.1 x87 FPU Floating-Point Exception Mask Bits The exception-flag mask bits (bits 0 through 5 of the x87 FPU control word) mask the 6 floating-point exception flags in the x87 FPU status word. When one of these mask bits is set, its corresponding x87 FPU floating-point exception is blocked from being generated. 8.1.5.2 Precision Control Field The precision-control (PC) field (bits 8 and 9 of the x87 FPU control word) determines the precision (64, 53, or 24 bits) of floating-point calculations made by the x87 FPU (see Table 8-2). The default precision is double extended precision, which uses the full 64-bi...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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