ia-32_volume1_basic-arch

Mm7 xmm registers xmm0 through xmm15 and the mxcsr

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: lative to stack or string destination. Destination of string instructions. Local Data Destination Strings DS ES Data Segment Data Segment pointed to with the ES register Vol. 1 3-29 BASIC EXECUTION ENVIRONMENT At the machine level, a segment override is specified with a segment-override prefix, which is a byte placed at the beginning of an instruction. The following default segment selections cannot be overridden: Instruction fetches must be made from the code segment. Destination strings in string instructions must be stored in the data segment pointed to by the ES register. Push and pop operations must always reference the SS segment. Some instructions require a segment selector to be specified explicitly. In these cases, the 16-bit segment selector can be located in a memory location or in a 16-bit register. For example, the following MOV instruction moves a segment selector located in register BX into segment register DS: MOV DS, BX Segment selectors can also be specified explicitly as part of a 48-bit far pointer in memory. Here, the first doubleword in memory contains the offset and the next word contains the segment selector. 3.7.4.1 Segmentation in 64-Bit Mode In IA-32e mode, the effects of segmentation depend on whether the processor is running in compatibility mode or 64-bit mode. In compatibility mode, segmentation functions just as it does in legacy IA-32 mode, using the 16-bit or 32-bit protected mode semantics described above. In 64-bit mode, segmentation is generally (but not completely) disabled, creating a flat 64-bit linear-address space. The processor treats the segment base of CS, DS, ES, SS as zero, creating a linear address that is equal to the effective address. The exceptions are the FS and GS segments, whose segment registers (which hold the segment base) can be used as additional base registers in some linear address calculations. 3.7.5 Specifying an Offset The offset part of a memory address can be specified directly as a static value (called a displacement) or through an address computation made up of one or more of the following components: Displacement -- An 8-, 16-, or 32-bit value. Base -- The value in a general-purpose register. Index -- The value in a general-purpose register. Scale factor -- A value of 2, 4, or 8 that is multiplied by the index value. The offset which results from adding these components is called an effective address. Each of these components can have either a positive or negative (2s complement) value, with the exception of the scaling factor. Figure 3-11 shows all 3-30 Vol. 1 BASIC EXECUTION ENVIRONMENT the possible ways that these components can be combined to create an effective address in the selected segment. Base EAX EBX ECX EDX ESP EBP ESI EDI Index EAX EBX ECX EDX EBP ESI EDI Scale 1 2 * 4 8 Displacement None + 8-bit 16-bit 32-bit + Offset = Base + (Index * Scale) + Displacement Figure 3-11. Offset (or Effective Address) Computation The uses of general-purpose registers as base or index co...
View Full Document

This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

Ask a homework question - tutors are online