Unformatted text preview: e effect of instruction prefixes on MMX instructions. Unpredictable behavior can range from being treated as a reserved operation on one generation of IA-32 processors to generating an invalid opcode exception on another generation of processors. Table 9-3. Effect of Prefixes on MMX Instructions
Prefix Type Address Size Prefix (67H) Effect on MMX Instructions Affects instructions with a memory operand. Reserved for instructions without a memory operand and may result in unpredictable behavior. Operand Size (66H) Segment Override (2EH, 36H, 3EH, 26H, 64H, 65H) Repeat Prefix (F3H) Repeat NE Prefix(F2H) Lock Prefix (F0H) Branch Hint Prefixes (2EH and 3EH) Reserved and may result in unpredictable behavior. Affects instructions with a memory operand. Reserved for instructions without a memory operand and may result in unpredictable behavior. Reserved and may result in unpredictable behavior. Reserved and may result in unpredictable behavior. Reserved; generates invalid opcode exception (#UD). Reserved and may result in unpredictable behavior. See "Instruction Prefixes" in Chapter 2, "Instruction Format," of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2A, for a description of the instruction prefixes. Vol. 1 9-15 PROGRAMMING WITH INTEL MMXTM TECHNOLOGY 9-16 Vol. 1 CHAPTER 10 PROGRAMMING WITH STREAMING SIMD EXTENSIONS (SSE)
The streaming SIMD extensions (SSE) were introduced into the IA-32 architecture in the Pentium III processor family. These extensions enhance the performance of IA-32 processors for advanced 2-D and 3-D graphics, motion video, image processing, speech recognition, audio synthesis, telephony, and video conferencing. This chapter describes SSE. Chapter 11, "Programming with Streaming SIMD Extensions 2 (SSE2)," provides information to assist in writing application programs that use SSE2 extensions. Chapter 12, "Programming with SSE3 and Supplemental SSE3," provides this information for SSE3 extensions. 10.1 OVERVIEW OF SSE EXTENSIONS Intel MMX technology introduced single-instruction multiple-data (SIMD) capability into the IA-32 architecture, with the 64-bit MMX registers, 64-bit packed integer data types, and instructions that allowed SIMD operations to be performed on packed integers. SSE extensions expand the SIMD execution model by adding facilities for handling packed and scalar single-precision floating-point values contained in 128-bit registers. If CPUID.01H:EDX.SSE[bit 25] = 1, SSE extensions are present. SSE extensions add the following features to the IA-32 architecture, while maintaining backward compatibility with all existing IA-32 processors, applications and operating systems. Eight 128-bit data registers (called XMM registers) in non-64-bit modes; sixteen XMM registers are available in 64-bit mode. The 32-bit MXCSR register, which provides control and status bits for operations performed on XMM registers. The 128-bit packed single-precision floating-poi...
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- Winter '11
- X86, Intel corporation, 64-bit mode, fpu floating-point exception, FPU Control Instructions