Unformatted text preview: ing-point values contained in XMM registers and on packed integers contained in MMX registers. Several SSE instructions provide state management, cache control, and memory ordering operations. Other SSE instructions are targeted at applications that operate on arrays of single-precision floating-point data elements (3-D geometry, 3-D rendering, and video encoding and decoding applications). SSE2 extensions were introduced in Pentium 4 and Intel Xeon processors. SSE2 instructions operate on packed double-precision floating-point values contained in XMM registers and on packed integers contained in MMX and XMM registers. SSE2 integer instructions extend IA-32 SIMD operations by adding new 128-bit SIMD integer operations and by expanding existing 64-bit SIMD integer operations to 128-bit XMM capability. SSE2 instructions also provide new cache control and memory ordering operations. SSE3 extensions were introduced with the Pentium 4 processor supporting HyperThreading Technology (built on 90 nm process technology). SSE3 offers 13 instructions that accelerate performance of Streaming SIMD Extensions technology, Streaming SIMD Extensions 2 technology, and x87-FP math capabilities. SSSE3 extensions were introduced with the Intel Xeon processor 5100 series and Intel Core 2 processor family. SSSE3 offers 32 instructions to accelerate processing of SIMD integer data. Intel 64 architecture allows four generations of 128-bit SIMD extensions to access up to 16 XMM registers. IA-32 architecture provides 8 XMM registers. See also: Section 5.4, "MMXTM Instructions," and Chapter 9, "Programming with Intel MMXTM Technology" Section 5.5, "SSE Instructions," and Chapter 10, "Programming with Streaming SIMD Extensions (SSE)" Section 5.6, "SSE2 Instructions," and Chapter 11, "Programming with Streaming SIMD Extensions 2 (SSE2)" Section 5.7, "SSE3 Instructions," and Chapter 12, "Programming with SSE3 and Supplemental SSE3" 2-16 Vol. 1 INTEL 64 AND IA-32 ARCHITECTURES SIMD Extension Register Layout MMX Registers Data Type MMX Technology 8 Packed Byte Integers 4 Packed Word Integers 2 Packed Doubleword Integers Quadword MMX Registers SSE 8 Packed Byte Integers 4 Packed Word Integers 2 Packed Doubleword Integers Quadword XMM Registers 4 Packed Single-Precision Floating-Point Values MMX Registers SSE2/SSE3/SSSE3 2 Packed Doubleword Integers Quadword XMM Registers 2 Packed Double-Precision Floating-Point Values 16 Packed Byte Integers 8 Packed Word Integers 4 Packed Doubleword Integers 2 Quadword Integers Double Quadword Figure 2-4. SIMD Extensions, Register Layouts, and Data Types Vol. 1 2-17 INTEL 64 AND IA-32 ARCHITECTURES 2.2.5 Hyper-Threading Technology Hyper-Threading (HT) Technology was developed to improve the performance of IA-32 processors when executing multi-threaded operating system and application code or single-threaded applications under multi-tasking environments. The technology enables...
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- Winter '11
- X86, Intel corporation, 64-bit mode, fpu floating-point exception, FPU Control Instructions