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Unformatted text preview: 32 Architectures Software Developer's Manual, Volume 3A, gives guidelines for integrating these extensions into an operating-system environment. 10-2 Vol. 1 PROGRAMMING WITH STREAMING SIMD EXTENSIONS (SSE) 10.2 SSE PROGRAMMING ENVIRONMENT Figure 10-1 shows the execution environment for the SSE extensions. All SSE instructions operate on the XMM registers, MMX registers, and/or memory as follows: XMM registers -- These eight registers (see Figure 10-2 and Section 10.2.2, "XMM Registers") are used to operate on packed or scalar single-precision floating-point data. Scalar operations are operations performed on individual (unpacked) single-precision floating-point values stored in the low doubleword of an XMM register. XMM registers are referenced by the names XMM0 through XMM7.
Address Space XMM Registers Eight 128-Bit 32 Bits 232 -1 MXCSR Register MMX Registers Eight 64-Bit General-Purpose Registers Eight 32-Bit 0 EFLAGS Register 32 Bits Figure 10-1. SSE Execution Environment MXCSR register -- This 32-bit register (see Figure 10-3 and Section 10.2.3, "MXCSR Control and Status Register") provides status and control bits used in SIMD floating-point operations. MMX registers -- These eight registers (see Figure 9-2) are used to perform operations on 64-bit packed integer data. They are also used to hold operands for some operations performed between the MMX and XMM registers. MMX registers are referenced by the names MM0 through MM7. General-purpose registers -- The eight general-purpose registers (see Figure 3-5) are used along with the existing IA-32 addressing modes to address operands in memory. (MMX and XMM registers cannot be used to address memory). The general-purpose registers are also used to hold operands for some Vol. 1 10-3 PROGRAMMING WITH STREAMING SIMD EXTENSIONS (SSE) SSE instructions and are referenced as EAX, EBX, ECX, EDX, EBP, ESI, EDI, and ESP. EFLAGS register -- This 32-bit register (see Figure 3-8) is used to record result of some compare operations. 10.2.1 SSE in 64-Bit Mode and Compatibility Mode In compatibility mode, SSE extensions function like they do in protected mode. In 64-bit mode, eight additional XMM registers are accessible. Registers XMM8-XMM15 are accessed by using REX prefixes. Memory operands are specified using the ModR/M, SIB encoding described in Section 3.7.5. Some SSE instructions may be used to operate on general-purpose registers. Use the REX.W prefix to access 64-bit general-purpose registers. Note that if a REX prefix is used when it has no meaning, the prefix is ignored. 10.2.2 XMM Registers Eight 128-bit XMM data registers were introduced into the IA-32 architecture with SSE extensions (see Figure 10-2). These registers can be accessed directly using the names XMM0 to XMM7; and they can be accessed independently from the x87 FPU and MMX registers and the general-purpose registers (that is, they are not aliased to any other of the processor's registers).
127 XMM7 XMM6 XMM5 XMM4 XMM3 XMM2 XM...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.
- Winter '11