Unformatted text preview: subsequent interrupts from interfering with the execution of the handler. When a handler is called through a trap gate, the state of the IF flag is not changed. Table 6-1. Exceptions and Interrupts
Vector No. 0 1 2 3 4 5 6 7 8 9 10 11 12 #BP #OF #BR #UD #NM #DF #MF #TS #NP #SS Mnemonic #DE #DB Debug NMI Interrupt Breakpoint Overflow BOUND Range Exceeded Invalid Opcode (UnDefined Opcode) Device Not Available (No Math Coprocessor) Double Fault CoProcessor Segment Overrun (reserved) Invalid TSS Segment Not Present Stack Segment Fault Description Divide Error Source DIV and IDIV instructions. Any code or data reference. Non-maskable external interrupt. INT 3 instruction. INTO instruction. BOUND instruction. UD2 instruction or reserved opcode.1 Floating-point or WAIT/FWAIT instruction. Any instruction that can generate an exception, an NMI, or an INTR. Floating-point instruction.2 Task switch or TSS access. Loading segment registers or accessing system segments. Stack operations and SS register loads. 6-14 Vol. 1 PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS Table 6-1. Exceptions and Interrupts (Contd.)
Vector No. 13 14 15 16 17 18 19 20-31 32-255 #MF #AC #MC #XF Mnemonic #GP #PF Description General Protection Page Fault Reserved Floating-Point Error (Math Fault) Alignment Check Machine Check SIMD Floating-Point Exception Reserved Maskable Interrupts External interrupt from INTR pin or INT n instruction. Floating-point or WAIT/FWAIT instruction. Any data reference in memory.3 Error codes (if any) and source are model dependent.4 SIMD Floating-Point Instruction5 Source Any memory reference and other protection checks. Any memory reference. NOTES: 1. The UD2 instruction was introduced in the Pentium Pro processor. 2. IA-32 processors after the Intel386 processor do not generate this exception. 3. This exception was introduced in the Intel486 processor. 4. This exception was introduced in the Pentium processor and enhanced in the P6 family processors. 5. This exception was introduced in the Pentium III processor. If the code segment for the handler procedure has the same privilege level as the currently executing program or task, the handler procedure uses the current stack; if the handler executes at a more privileged level, the processor switches to the stack for the handler's privilege level. If no stack switch occurs, the processor does the following when calling an interrupt or exception handler (see Figure 6-5): 1. Pushes the current contents of the EFLAGS, CS, and EIP registers (in that order) on the stack. 2. Pushes an error code (if appropriate) on the stack. 3. Loads the segment selector for the new code segment and the new instruction pointer (from the interrupt gate or trap gate) into the CS and EIP registers, respectively. 4. If the call is through an interrupt gate, clears the IF flag in the EFLAGS register. 5. Begins execution of the handler procedure. Vol. 1 6-15 PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS Interrupted Procedure's and Handler...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.
- Winter '11