ia-32_volume1_basic-arch

Simd operations these extensions include the mmx

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Unformatted text preview: e logical instructions perform AND, AND NOT, OR, and XOR operations on quadword operands. PAND PANDN POR PXOR Bitwise logical AND Bitwise logical AND NOT Bitwise logical OR Bitwise logical exclusive OR 5.4.6 MMX Shift and Rotate Instructions The shift and rotate instructions shift and rotate packed bytes, words, or doublewords, or quadwords in 64-bit operands. PSLLW PSLLD PSLLQ PSRLW PSRLD PSRLQ PSRAW PSRAD Shift packed words left logical Shift packed doublewords left logical Shift packed quadword left logical Shift packed words right logical Shift packed doublewords right logical Shift packed quadword right logical Shift packed words right arithmetic Shift packed doublewords right arithmetic 5.4.7 EMMS MMX State Management Instructions Empty MMX state The EMMS instruction clears the MMX state from the MMX registers. 5.5 SSE INSTRUCTIONS SSE instructions represent an extension of the SIMD execution model introduced with the MMX technology. For more detail on these instructions, see Chapter 10, "Programming with Streaming SIMD Extensions (SSE)." SSE instructions can only be executed on Intel 64 and IA-32 processors that support SSE extensions. Support for these instructions can be detected with the CPUID instruction. See the description of the CPUID instruction in Chapter 3, "Instruction Set Reference, A-M," of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2A. 5-16 Vol. 1 INSTRUCTION SET SUMMARY SSE instructions are divided into four subgroups (note that the first subgroup has subordinate subgroups of its own): SIMD single-precision floating-point instructions that operate on the XMM registers MXSCR state management instructions 64-bit SIMD integer instructions that operate on the MMX registers Cacheability control, prefetch, and instruction ordering instructions The following sections provide an overview of these groups. 5.5.1 SSE SIMD Single-Precision Floating-Point Instructions These instructions operate on packed and scalar single-precision floating-point values located in XMM registers and/or memory. This subgroup is further divided into the following subordinate subgroups: data transfer, packed arithmetic, comparison, logical, shuffle and unpack, and conversion instructions. 5.5.1.1 SSE Data Transfer Instructions SSE data transfer instructions move packed and scalar single-precision floating-point operands between XMM registers and between XMM registers and memory. MOVAPS Move four aligned packed single-precision floating-point values between XMM registers or between and XMM register and memory Move four unaligned packed single-precision floating-point values between XMM registers or between and XMM register and memory Move two packed single-precision floating-point values to an from the high quadword of an XMM register and memory Move two packed single-precision floating-point values from the high quadword of an XMM register to the low quadword of another XMM register Move two packed single-precision floating-p...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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