ia-32_volume1_basic-arch

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Unformatted text preview: tion operand forming an intermediate value of twice the width of an operand. The result is extracted from the intermediate value into the destination operand by selecting the 128 bit or 64 bit value that are right-aligned to the byte offset specified by the immediate value. 5.9 LGDT SGDT LLDT SLDT LTR STR LIDT SIDT MOV LMSW SMSW CLTS ARPL LAR LSL VERR VERW MOV INVD WBINVD INVLPG SYSTEM INSTRUCTIONS Load global descriptor table (GDT) register Store global descriptor table (GDT) register Load local descriptor table (LDT) register Store local descriptor table (LDT) register Load task register Store task register Load interrupt descriptor table (IDT) register Store interrupt descriptor table (IDT) register Load and store control registers Load machine status word Store machine status word Clear the task-switched flag Adjust requested privilege level Load access rights Load segment limit Verify segment for reading Verify segment for writing Load and store debug registers Invalidate cache, no writeback Invalidate cache, with writeback Invalidate TLB Entry The following system instructions are used to control those functions of the processor that are provided to support for operating systems and executives. 5-30 Vol. 1 INSTRUCTION SET SUMMARY LOCK (prefix) HLT RSM RDMSR WRMSR RDPMC RDTSC SYSENTER SYSEXIT Lock Bus Halt processor Return from system management mode (SMM) Read model-specific register Write model-specific register Read performance monitoring counters Read time stamp counter Fast System Call, transfers to a flat protected mode kernel at CPL = 0 Fast System Call, transfers to a flat protected mode kernel at CPL = 3 5.10 CDQE CMPSQ 64-BIT MODE INSTRUCTIONS Convert doubleword to quadword Compare string operands Compare RDX:RAX with m128 Load qword at address (R)SI into RAX Move qword from address (R)SI to (R)DI Move doubleword to quadword, zero-extension Store RAX at address RDI Exchanges current GS base register value with value in MSR address C0000102H Fast call to privilege level 0 system procedures Return from fast system call The following instructions are introduced in 64-bit mode. This mode is a sub-mode of IA-32e mode. CMPXCHG16B LODSQ MOVSQ MOVZX (64-bits) STOSQ SWAPGS SYSCALL SYSRET 5.11 VIRTUAL-MACHINE EXTENSIONS The behavior of the VMCS-maintenance instructions is summarized below: VMPTRLD VMPTRST VMCLEAR Takes a single 64-bit source operand in memory. It makes the referenced VMCS active and current. Takes a single 64-bit destination operand that is in memory. Current-VMCS pointer is stored into the destination operand. Takes a single 64-bit operand in memory. The instruction sets the launch state of the VMCS referenced by the operand to "clear", renders that VMCS inactive, and ensures that data for Vol. 1 5-31 INSTRUCTION SET SUMMARY the VMCS have been written to the VMCS-data area in the referenced VMCS region. VMREAD Reads a component from the VMCS (the encoding of that field is given in a register operand) and stores it into a destinatio...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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