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Unformatted text preview: hat use software task switching1 can set the TS bit by reading CR0, ORing a "1" into2 bit 3, and writing back CR0. Any subsequent floating-point instructions (now being executed in a new thread context) will fault via interrupt 7 before execution. This allows a DNA handler to save the old floating-point context and reload the x87 FPU state for the current thread. The handler should clear the TS bit before exit using the CLTS instruction. On return from the handler the faulting thread will proceed with its floating-point computation. Some operating systems save the x87 FPU context on every task switch, typically because they also change the linear address space between tasks. The problem and solution discussed in the following sections apply to these operating systems also. 1. In a software task switch, the operating system uses a sequence of instructions to save the suspending thread's state and restore the resuming thread's state, instead of the single long noninterruptible task switch operation provided by the IA-32 architecture. 2. Although CR0, bit 2, the emulation flag (EM), also causes a DNA exception, do not use the EM bit as a surrogate for TS. EM means that no x87 FPU is available and that floating-point instructions must be emulated. Using EM to trap on task switches is not compatible with the MMX technology. If the EM flag is set, MMX instructions raise the invalid opcode exception. D-24 Vol. 1 GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS D.3.6.2 Tracking x87 FPU Ownership Since the contents of the x87 FPU may not belong to the currently executing thread, the thread identifier for the last x87 FPU user needs to be tracked separately. This is not complicated; the kernel should simply provide a variable to store the thread identifier of the x87 FPU owner, separate from the variable that stores the identifier for the currently executing thread. This variable is updated in the DNA exception handler, and is used by the DNA exception handler to find the x87 FPU save areas of the old and new threads. A simplified flow for a DNA exception handler is then: 1. Use the "x87 FPU Owner" variable to find the x87 FPU save area of the last thread to use the x87 FPU. 2. Save the x87 FPU contents to the old thread's save area, typically using an FNSAVE or FXSAVE instruction. 3. Set the x87 FPU Owner variable to the identify the currently executing thread. 4. Reload the x87 FPU contents from the new thread's save area, typically using an FRSTOR or FXSTOR instruction. 5. Clear TS using the CLTS instruction and exit the DNA exception handler. While this flow covers the basic requirements for speculatively deferred x87 FPU state swaps, there are some additional subtleties that need to be handled in a robust implementation. D.3.6.3 Interaction of x87 FPU State Saves and Floating-Point Exception Association Recall these key points from earlier in this document: When considering floatingpoint exceptions across all implementations of th...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.
- Winter '11