Unformatted text preview: memory, memory reordering does not occur externally at the processor's pins (that is, reads and writes appear in-order). Designating a memory mapped I/O region of the address space as uncacheable insures that reads and writes of I/O devices are carried out in program order. See Chapter 10, "Memory Cache Control," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, for more information on using MTRRs. Another method of enforcing program order is to insert one of the serializing instructions, such as the CPUID instruction, between operations. See Chapter 7, "MultipleProcessor Management," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, for more information on serialization of instructions. It should be noted that the chip set being used to support the processor (bus controller, memory controller, and/or I/O controller) may post writes to uncacheable memory which can lead to out-of-order execution of memory accesses. In situations where out-of-order processing of memory accesses by the chip set can potentially cause faulty memory-mapped I/O processing, code must be written to force synchronization and ordering of I/O operations. Serializing instructions can often be used for this purpose. Vol. 1 13-7 INPUT/OUTPUT When the I/O address space is used instead of memory-mapped I/O, the situation is different in two respects: The processor never buffers I/O writes. Therefore, strict ordering of I/O operations is enforced by the processor. (As with memory-mapped I/O, it is possible for a chip set to post writes in certain I/O ranges.) The processor synchronizes I/O instruction execution with external bus activity (see Table 13-1). Table 13-1. I/O Instruction Serialization
Processor Delays Execution of ... Instruction Being Current Executed Instruction? IN INS REP INS OUT OUTS REP OUTS Yes Yes Yes Yes Yes Yes Next Instruction? Until Completion of ... Pending Stores? Yes Yes Yes Yes Yes Yes Current Store? Yes Yes Yes 13-8 Vol. 1 CHAPTER 14 PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION
When writing software intended to run on IA-32 processors, it is necessary to identify the type of processor present in a system and the processor features that are available to an application. 14.1 USING THE CPUID INSTRUCTION Use the CPUID instruction for processor identification in the Pentium M processor family, Pentium 4 processor family, Intel Xeon processor family, P6 family, Pentium processor, and later Intel486 processors. This instruction returns the family, model and (for some processors) a brand string for the processor that executes the instruction. It also indicates the features that are present in the processor and give information about the processors caches and TLB. The ID flag (bit 21) in the EFLAGS register indicates support for the CPUID instruction. If a software procedure can set and clear this flag, the processor executing the procedure supports the CPUID instruction. The CPUID...
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- Winter '11
- X86, Intel corporation, 64-bit mode, fpu floating-point exception, FPU Control Instructions