Unformatted text preview: nstructions -- see Table C-3 SSE2 instructions -- see Table C-4 SSE3 instructions -- see Table C-5 Table C-1 lists types of floating-point exceptions that potentially can be generated by the x87 FPU and by SSE/SSE2/SSE3 instructions. Table C-1. x87 FPU and SIMD Floating-Point Exceptions
Floatingpoint Exception #IS #IA or #I #D #Z #O #U #P Description Invalid-operation exception for stack underflow or stack overflow (can only be generated for x87 FPU instructions)* Invalid-operation exception for invalid arithmetic operands and unsupported formats* Denormal-operand exception Divide-by-zero exception Numeric-overflow exception Numeric-underflow exception Inexact-result (precision) exception NOTE: * The x87 FPU instruction set generates two types of invalid-operation exceptions: #IS (stack underflow or stack overflow) and #IA (invalid arithmetic operation due to invalid arithmetic operands or unsupported formats). SSE/SSE2/SSE3 instructions potentially generate #I (invalid operation exceptions due to invalid arithmetic operands or unsupported formats). The floating point exceptions shown in Table C-1 (except for #D and #IS) are defined in IEEE Standard 754-1985 for Binary Floating-Point Arithmetic. See Section 4.9.1, "Floating-Point Exception Conditions," for a detailed discussion of floating-point exceptions. Vol. 1 C-1 FLOATING-POINT EXCEPTIONS SUMMARY C.2 X87 FPU INSTRUCTIONS Table C-2 lists the x87 FPU instructions in alphabetical order. For each instruction, it summarizes the floating-point exceptions that the instruction can generate. Table C-2. Exceptions Generated with x87 FPU Floating-Point Instructions
Mnemonic F2XM1 FABS FADD(P) FBLD FBSTP FCHS FCLEX FCMOVcc FCOM, FCOMP, FCOMPP FCOMI, FCOMIP, FUCOMI, FUCOMIP FCOS FDECSTP FDIV(R)(P) FFREE FIADD FICOM(P) FIDIV FIDIVR FILD FIMUL FINCSTP FINIT FIST(P) FISTTP FISUB(R) Instruction Exponential Absolute value Add floating-point BCD load BCD store and pop Change sign Clear exceptions Floating-point conditional move Compare floating-point Compare floating-point and set EFLAGS Cosine Decrement stack pointer Divide floating-point Free register Integer add Integer compare Integer divide Integer divide reversed Integer load Integer multiply Increment stack pointer Initialize processor Integer store Truncate to integer (SSE3 instruction) Integer subtract Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y #IS #IA Y Y Y Y Y Y Y Y Y Y Y Y Y Y #D Y #Z #O #U Y #P Y C-2 Vol. 1 FLOATING-POINT EXCEPTIONS SUMMARY Table C-2. Exceptions Generated with x87 FPU Floating-Point Instructions (Contd.)
Mnemonic FLD extended or stack FLD single or double FLD1 FLDCW FLDENV FLDL2E FLDL2T FLDLG2 FLDLN2 FLDPI FLDZ FMUL(P) FNOP FPATAN FPREM FPREM1 FPTAN FRNDINT FRSTOR FSAVE FSCALE FSIN FSINCOS FSQRT FST(P) stack or extended FST(P) single or double FSTCW FSTENV FSTSW (AX) FSUB(R)(P) FTST Instruction Load floating-point Load floating-point Load + 1.0 Loa...
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- Winter '11
- X86, Intel corporation, 64-bit mode, fpu floating-point exception, FPU Control Instructions