ia-32_volume1_basic-arch

Thermal manager 2 6 intel core 2 extreme processor

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Unformatted text preview: ching of, 10-18 description, 10-18 temporal vs. non-temporal data, 10-18 Non-waiting instructions, x87 FPU, 8-33, 8-45 NOP instruction, 7-32 Normalized finite number, 4-6, 4-16, 4-18 NOT instruction, 7-14 Notation bit and byte order, 1-4 exceptions, 1-9 hexadecimal and binary numbers, 1-6 instruction operands, 1-6 notational conventions, 1-4 reserved bits, 1-5 segmented addressing, 1-6 NT (nested task) flag, EFLAGS register, 3-23, A-1 Numeric overflow exception (#O) overview, 4-27 SSE and SSE2 extensions, 11-22 x87 FPU, 8-7, 8-40 Numeric underflow exception (#U) overview, 4-28 SSE and SSE2 extensions, 11-22 x87 FPU, 8-7, 8-41 ORPS instruction, 10-13 OSFXSR flag, control register CR4, 11-28 OSXMMEXCPT flag control register CR4, 11-25, 11-28 OUT instruction, 5-8, 7-27, 13-4 OUTS instruction, 5-8, 7-27, 13-4 Overflow exception (#OF), 6-18 Overflow, x87 FPU stack, 8-36, 8-37 P P6 family microarchitecture description of, 2-7 history of, 2-3 P6 family processors description of, 1-1 history of, 2-3 P6 family microarchitecture, 2-7 PABSB instruction, 5-29, 12-11 PABSD instruction, 12-11 PABSW instruction, 5-29, 12-11 Packed BCD integer indefinite, 4-13 BCD integers, 4-12 bytes, 9-3 doublewords, 9-3 SIMD data types, 4-10 SIMD floating-point values, 4-11 SIMD integers, 4-10, 4-11 words, 9-3 PACKSSWB instruction, 9-9 PACKUSWB instruction, 9-9 PADDB instruction, 9-8 PADDD instruction, 9-8 PADDQ instruction, 11-15 PADDSB instruction, 9-8 PADDSW instruction, 9-8 PADDUSB instruction, 9-8 PADDUSW instruction, 9-8 PADDW instruction, 9-8 PALIGNR instruction, 5-30, 12-13 PAND instruction, 9-10 PANDN instruction, 9-10 Parameter passing argument list, 6-8 on stack, 6-7 on the stack, 6-7 through general-purpose registers, 6-7 x87 FPU register stack, 8-5 XMM registers, 11-34 PAUSE instruction, 11-18 PAVGB instruction, 10-16 PC (precision) field, x87 FPU control word, 8-11 PCMPEQB instruction, 9-9 PCMPEQD instruction, 9-9 PCMPEQW instruction, 9-9 PCMPGTB instruction, 9-9 PCMPGTD instruction, 9-9 O OE (numeric overflow exception) flag MXCSR register, 11-22 x87 FPU status word, 8-7, 8-40 OF (overflow) flag EFLAGS register, 3-21, 6-18 OF (overflow) flag, EFLAGS register, A-1 Offset (operand addressing), 3-30 Offset (operand addressing, 64-bit mode), 3-32 OM (numeric overflow exception) mask bit MXCSR register, 11-22 x87 FPU control word, 8-11, 8-40 Operand addressing, modes, 3-26 instruction, 1-6 size attribute, 3-24 sizes, 3-11, 3-25 x87 FPU instructions, 8-22 OR instruction, 7-14 Ordering I/O, 13-7 ORPD instruction, 11-10 INDEX-10 Vol. 1 INDEX PCMPGTW instruction, 9-9 PE (inexact result exception) flag, 11-23 MXCSR register, 4-23 x87 FPU status word, 4-23, 8-7, 8-43 Pentium 4 processor, 1-1 description of, 2-4, 2-5 Pentium 4 processor supporting Hyper-Threading Technology description of, 2-4, 2-5 Pentium II processor, 1-2 description of, 2-3 P6 family microarchitecture, 2-7 Pentium II Xeon processor description of, 2-3 Pentium III processor, 1-2 description of, 2-4 P6 family micr...
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