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Unformatted text preview: I Y Y Y #D Y Y Y #Z #O Y Y #U Y Y #P Y Y UNPCKHPD UNPCKLPD XORPD C.5 SSE3 INSTRUCTIONS Table C-5 lists the SSE3 instructions that have at least one of the following characteristics: have floating-point operands generate floating-point results For each instruction, the table summarizes the floating-point exceptions that the instruction can generate. Table C-5. Exceptions Generated with SSE3 Instructions
Instruction ADDSUBPD Description Add /Sub packed DP FP numbers from XMM2/Mem to XMM1. Add /Sub packed SP FP numbers from XMM2/Mem to XMM1. #I Y #D Y #Z #O Y #U Y #P Y ADDSUBPS Y Y Y Y Y Vol. 1 C-11 FLOATING-POINT EXCEPTIONS SUMMARY Table C-5. Exceptions Generated with SSE3 Instructions (Contd.)
Instruction FISTTP HADDPD Description See Table C-2. Add horizontally packed DP FP numbers XMM2/Mem to XMM1. Add horizontally packed SP FP numbers XMM2/Mem to XMM1 Sub horizontally packed DP FP numbers XMM2/Mem to XMM1 Sub horizontally packed SP FP numbers XMM2/Mem to XMM1 Load unaligned integer 128bit. Move 64 bits representing one DP data from XMM2/Mem to XMM1 and duplicate. Move 128 bits representing 4 SP data from XMM2/Mem to XMM1 and duplicate high. Move 128 bits representing 4 SP data from XMM2/Mem to XMM1 and duplicate low. #I Y Y Y Y Y #D #Z #O #U #P Y Y HADDPS Y Y Y Y Y HSUBPD Y Y Y Y Y HSUBPS Y Y Y Y Y LDDQU MOVDDUP MOVSHDUP MOVSLDUP C.6 SSSE3 INSTRUCTIONS SSSE3 instructions operate on integer data elements. They do not generate floatingpoint exceptions. C-12 Vol. 1 APPENDIX D GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS
As described in Chapter 8, "Programming with the x87 FPU," the IA-32 Architecture supports two mechanisms for accessing exception handlers to handle unmasked x87 FPU exceptions: native mode and MS-DOS compatibility mode. The primary purpose of this appendix is to provide detailed information to help software engineers design and write x87 FPU exception-handling facilities to run on PC systems that use the MS-DOS compatibility mode1 for handling x87 FPU exceptions. Some of the information in this appendix will also be of interest to engineers who are writing native-mode x87 FPU exception handlers. The information provided is as follows: Discussion of the origin of the MS-DOS x87 FPU exception handling mechanism and its relationship to the x87 FPU's native exception handling mechanism. Description of the IA-32 flags and processor pins that control the MS-DOS x87 FPU exception handling mechanism. Description of the external hardware typically required to support MS-DOS exception handling mechanism. Description of the x87 FPU's exception handling mechanism and the typical protocol for x87 FPU exception handlers. Code examples that demonstrate various levels of x87 FPU exception handlers. Discussion of x87 FPU considerations in multitasking environments. Discussion of native mode x87 FPU exception handling. The information given is oriented toward the most recent generations of IA-32 processors, starting with the Intel486. It...
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- Winter '11