Unformatted text preview: of this discussion, these instructions are further divided into subordinate subgroups of instructions that provide for: Address computations Table lookup Vol. 1 7-31 PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS Processor identification NOP and undefined instruction entry 22.214.171.124 Address Computation Instruction The LEA (load effective address) instruction computes the effective address in memory (offset within a segment) of a source operand and places it in a generalpurpose register. This instruction can interpret any of the processor's addressing modes and can perform any indexing or scaling that may be needed. It is especially useful for initializing the ESI or EDI registers before the execution of string instructions or for initializing the EBX register before an XLAT instruction. 126.96.36.199 Table Lookup Instructions The XLAT and XLATB (table lookup) instructions replace the contents of the AL register with a byte read from a translation table in memory. The initial value in the AL register is interpreted as an unsigned index into the translation table. This index is added to the contents of the EBX register (which contains the base address of the table) to calculate the address of the table entry. These instructions are used for applications such as converting character codes from one alphabet into another (for example, an ASCII code could be used to look up its EBCDIC equivalent in a table). 188.8.131.52 Processor Identification Instruction The CPUID (processor identification) instruction returns information about the processor on which the instruction is executed. 184.108.40.206 No-Operation and Undefined Instructions The NOP (no operation) instruction increments the EIP register to point at the next instruction, but affects nothing else. The UD2 (undefined) instruction generates an invalid opcode exception. Intel reserves the opcode for this instruction for this function. The instruction is provided to allow software to test an invalid opcode exception handler. 7-32 Vol. 1 CHAPTER 8 PROGRAMMING WITH THE X87 FPU
The x87 Floating-Point Unit (FPU) provides high-performance floating-point processing capabilities for use in graphics processing, scientific, engineering, and business applications. It supports the floating-point, integer, and packed BCD integer data types and the floating-point processing algorithms and exception handling architecture defined in the IEEE Standard 754 for Binary Floating-Point Arithmetic. This chapter describes the x87 FPU's execution environment and instruction set. It also provides exception handling information that is specific to the x87 FPU. Refer to the following chapters or sections of chapters for additional information about x87 FPU instructions and floating-point operations: Intel 64 and IA-32 Architectures Software Developer's Manual, Volumes 2A & 2B, provide detailed descriptions of x87 FPU instructions. Section 4.2.2, "Floating-Point Data Types," Section 220.127.116.11, "Signed Integers," and Section 4....
View Full Document
- Winter '11
- X86, Intel corporation, 64-bit mode, fpu floating-point exception, FPU Control Instructions