ia-32_volume1_basic-arch

Word tag word fpu instruction pointer offset fpu

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Unformatted text preview: nvalid operation when storing an integer value in memory with an FIST/FISTP instruction and the invalidoperation exception is masked, the x87 FPU stores the integer indefinite encoding in the destination operand as a masked response to the exception. In situations where the origin of a value with this encoding may be ambiguous, the invalid-operation exception flag can be examined to see if the value was produced as a response to an exception. 8.2.2 Unsupported Double Extended-Precision Floating-Point Encodings and Pseudo-Denormals The double extended-precision floating-point format permits many encodings that do not fall into any of the categories shown in Table 4-3. Table 8-3 shows these unsupported encodings. Some of these encodings were supported by the Intel 287 math coprocessor; however, most of them are not supported by the Intel 387 math coprocessor and later IA-32 processors. These encodings are no longer supported due to changes made in the final version of IEEE Standard 754 that eliminated these encodings. Specifically, the categories of encodings formerly known as pseudo-NaNs, pseudoinfinities, and un-normal numbers are not supported and should not be used as operand values. The Intel 387 math coprocessor and later IA-32 processors generate an invalid-operation exception when these encodings are encountered as operands. Beginning with the Intel 387 math coprocessor, the encodings formerly known as pseudo-denormal numbers are not generated by IA-32 processors. When encountered as operands, however, they are handled correctly; that is, they are treated as denormals and a denormal exception is generated. Pseudo-denormal numbers should not be used as operand values. They are supported by current IA-32 processors (as described here) to support legacy code. 8-20 Vol. 1 PROGRAMMING WITH THE X87 FPU Table 8-3. Unsupported Double Extended-Precision Floating-Point Encodings and Pseudo-Denormals Class Positive Pseudo-NaNs Quiet Sign 0 . 0 0 . 0 0 0 . 0 0 . 0 1 . 1 1 . 1 1 1 . 1 1 . 1 Biased Exponent 11..11 . 11..11 11..11 . 11..11 11..11 11..10 . 00..01 00..00 . 00..00 00..00 . 00..00 11..10 . 00..01 11..11 11..11 . 11..11 11..11 . 11..11 Significand Integer 0 Fraction 11..11 . 10..00 01..11 . 00..01 00..00 11..11 . 00..00 11..11 . 00..00 11..11 . 00..00 11..01 . 00..00 00..00 01..11 . 00..01 11..11 . 10..00 Signaling Positive Floating Point Pseudo-infinity Unnormals Pseudo-denormals 0 0 0 1 Negative Floating Point Pseudo-denormals 1 Unnormals Pseudo-infinity Negative Pseudo-NaNs Signaling 0 0 0 Quiet 0 15 bits 63 bits Vol. 1 8-21 PROGRAMMING WITH THE X87 FPU 8.3 X86 FPU INSTRUCTION SET The floating-point instructions that the x87 FPU supports can be grouped into six functional categories: Data transfer instructions Basic arithmetic instructions Comparison instructions Transcendental instructions Load constant instructions x87 FPU control instructions See Section 5.2, "x87 FPU Instructions," for a list of the floating-point instructions...
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