ia-32_volume1_basic-arch

Xmm register and memory move four unaligned packed

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Unformatted text preview: or interleave single-precision floatingpoint values in packed single-precision floating-point operands. SHUFPS UNPCKHPS UNPCKLPS Shuffles values in packed single-precision floating-point operands Unpacks and interleaves the two high-order values from two single-precision floating-point operands Unpacks and interleaves the two low-order values from two single-precision floating-point operands 5.5.1.6 SSE Conversion Instructions SSE conversion instructions convert packed and individual doubleword integers into packed and scalar single-precision floating-point values and vice versa. CVTPI2PS CVTSI2SS CVTPS2PI CVTTPS2PI CVTSS2SI CVTTSS2SI Convert packed doubleword integers to packed single-precision floating-point values Convert doubleword integer to scalar single-precision floatingpoint value Convert packed single-precision floating-point values to packed doubleword integers Convert with truncation packed single-precision floating-point values to packed doubleword integers Convert a scalar single-precision floating-point value to a doubleword integer Convert with truncation a scalar single-precision floating-point value to a scalar doubleword integer Vol. 1 5-19 INSTRUCTION SET SUMMARY 5.5.2 SSE MXCSR State Management Instructions MXCSR state management instructions allow saving and restoring the state of the MXCSR control and status register. LDMXCSR STMXCSR Load MXCSR register Save MXCSR register state 5.5.3 SSE 64-Bit SIMD Integer Instructions These SSE 64-bit SIMD integer instructions perform additional operations on packed bytes, words, or doublewords contained in MMX registers. They represent enhancements to the MMX instruction set described in Section 5.4, "MMXTM Instructions." PAVGB PAVGW PEXTRW PINSRW PMAXUB PMAXSW PMINUB PMINSW PMOVMSKB PMULHUW PSADBW PSHUFW Compute average of packed unsigned byte integers Compute average of packed unsigned word integers Extract word Insert word Maximum of packed unsigned byte integers Maximum of packed signed word integers Minimum of packed unsigned byte integers Minimum of packed signed word integers Move byte mask Multiply packed unsigned integers and store high result Compute sum of absolute differences Shuffle packed integer word in MMX register 5.5.4 SSE Cacheability Control, Prefetch, and Instruction Ordering Instructions The cacheability control instructions provide control over the caching of nontemporal data when storing data from the MMX and XMM registers to memory. The PREFETCHh allows data to be prefetched to a selected cache level. The SFENCE instruction controls instruction ordering on store operations. MASKMOVQ MOVNTQ MOVNTPS Non-temporal store of selected bytes from an MMX register into memory Non-temporal store of quadword from an MMX register into memory Non-temporal store of four packed single-precision floatingpoint values from an XMM register into memory 5-20 Vol. 1 INSTRUCTION SET SUMMARY PREFETCHh SFENCE Load 32 or more of bytes from memory to a selected level of the proc...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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