Xmm registers mmx registers andor memory as follows

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Unformatted text preview: asked if the corresponding mask bit is set, and it is unmasked if the bit is clear. These mask bits are set upon a power-up or reset. This causes all SIMD floating-point exceptions to be initially masked. If LDMXCSR or FXRSTOR clears a mask bit and sets the corresponding exception flag bit, a SIMD floating-point exception will not be generated as a result of this change. The unmasked exception will be generated only upon the execution of the next SSE/SSE2/SSE3 instruction that detects the unmasked exception condition. For more information about the use of the SIMD floating-point exception mask and flag bits, see Section 11.5, "SSE, SSE2, and SSE3 Exceptions," and Section 12.8, "SSE3/SSSE3 Exceptions." SIMD Floating-Point Rounding Control Field Bits 13 and 14 of the MXCSR register (the rounding control [RC] field) control how the results of SIMD floating-point instructions are rounded. See Section 4.8.4, 10-6 Vol. 1 PROGRAMMING WITH STREAMING SIMD EXTENSIONS (SSE) "Rounding," for a description of the function and encoding of the rounding control bits. Flush-To-Zero Bit 15 (FZ) of the MXCSR register enables the flush-to-zero mode, which controls the masked response to a SIMD floating-point underflow condition. When the underflow exception is masked and the flush-to-zero mode is enabled, the processor performs the following operations when it detects a floating-point underflow condition: Returns a zero result with the sign of the true result Sets the precision and underflow exception flags If the underflow exception is not masked, the flush-to-zero bit is ignored. The flush-to-zero mode is not compatible with IEEE Standard 754. The IEEEmandated masked response to underflow is to deliver the denormalized result (see Section, "Normalized and Denormalized Finite Numbers"). The flush-to-zero mode is provided primarily for performance reasons. At the cost of a slight precision loss, faster execution can be achieved for applications where underflows are common and rounding the underflow result to zero can be tolerated. The flush-to-zero bit is cleared upon a power-up or reset of the processor, disabling the flush-to-zero mode. Denormals-Are-Zeros Bit 6 (DAZ) of the MXCSR register enables the denormals-are-zeros mode, which controls the processor's response to a SIMD floating-point denormal operand condition. When the denormals-are-zeros flag is set, the processor converts all denormal source operands to a zero with the sign of the original operand before performing any computations on them. The processor does not set the denormal-operand exception flag (DE), regardless of the setting of the denormal-operand exception mask bit (DM); and it does not generate a denormal-operand exception if the exception is unmasked. The denormals-are-zeros mode is not compatible with IEEE Standard 754 (see Section, "Normalized and Denormalized Finite Numbers"). The denormalsare-zero...
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