Unformatted text preview: asked if the corresponding mask bit is set, and it is unmasked if the bit is clear. These mask bits are set upon a powerup or reset. This causes all SIMD floatingpoint exceptions to be initially masked. If LDMXCSR or FXRSTOR clears a mask bit and sets the corresponding exception flag bit, a SIMD floatingpoint exception will not be generated as a result of this change. The unmasked exception will be generated only upon the execution of the next SSE/SSE2/SSE3 instruction that detects the unmasked exception condition. For more information about the use of the SIMD floatingpoint exception mask and flag bits, see Section 11.5, "SSE, SSE2, and SSE3 Exceptions," and Section 12.8, "SSE3/SSSE3 Exceptions." 10.2.3.2 SIMD FloatingPoint Rounding Control Field Bits 13 and 14 of the MXCSR register (the rounding control [RC] field) control how the results of SIMD floatingpoint instructions are rounded. See Section 4.8.4, 106 Vol. 1 PROGRAMMING WITH STREAMING SIMD EXTENSIONS (SSE) "Rounding," for a description of the function and encoding of the rounding control bits. 10.2.3.3 FlushToZero Bit 15 (FZ) of the MXCSR register enables the flushtozero mode, which controls the masked response to a SIMD floatingpoint underflow condition. When the underflow exception is masked and the flushtozero mode is enabled, the processor performs the following operations when it detects a floatingpoint underflow condition: Returns a zero result with the sign of the true result Sets the precision and underflow exception flags If the underflow exception is not masked, the flushtozero bit is ignored. The flushtozero mode is not compatible with IEEE Standard 754. The IEEEmandated masked response to underflow is to deliver the denormalized result (see Section 4.8.3.2, "Normalized and Denormalized Finite Numbers"). The flushtozero mode is provided primarily for performance reasons. At the cost of a slight precision loss, faster execution can be achieved for applications where underflows are common and rounding the underflow result to zero can be tolerated. The flushtozero bit is cleared upon a powerup or reset of the processor, disabling the flushtozero mode. 10.2.3.4 DenormalsAreZeros Bit 6 (DAZ) of the MXCSR register enables the denormalsarezeros mode, which controls the processor's response to a SIMD floatingpoint denormal operand condition. When the denormalsarezeros flag is set, the processor converts all denormal source operands to a zero with the sign of the original operand before performing any computations on them. The processor does not set the denormaloperand exception flag (DE), regardless of the setting of the denormaloperand exception mask bit (DM); and it does not generate a denormaloperand exception if the exception is unmasked. The denormalsarezeros mode is not compatible with IEEE Standard 754 (see Section 4.8.3.2, "Normalized and Denormalized Finite Numbers"). The denormalsarezero...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.
 Winter '11
 Watlins

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