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Unformatted text preview: A-32 architecture. Protected mode uses the segment register content as selectors or pointers into descriptor tables. Descriptors provide 24-bit base addresses with a physical memory size of up to 16 MBytes, support for virtual memory management on a segment swapping basis, and a number of protection mechanisms. These mechanisms include: Segment limit checking Vol. 1 2-1 INTEL 64 AND IA-32 ARCHITECTURES Read-only and execute-only segment options Four privilege levels 2.1.3 The Intel386TM Processor (1985) The Intel386 processor was the first 32-bit processor in the IA-32 architecture family. It introduced 32-bit registers for use both to hold operands and for addressing. The lower half of each 32-bit Intel386 register retains the properties of the 16-bit registers of earlier generations, permitting backward compatibility. The processor also provides a virtual-8086 mode that allows for even greater efficiency when executing programs created for 8086/8088 processors. In addition, the Intel386 processor has support for: A 32-bit address bus that supports up to 4-GBytes of physical memory A segmented-memory model and a flat memory model Paging, with a fixed 4-KByte page size providing a method for virtual memory management Support for parallel stages 2.1.4 The Intel486TM Processor (1989) The Intel486TM processor added more parallel execution capability by expanding the Intel386 processor's instruction decode and execution units into five pipelined stages. Each stage operates in parallel with the others on up to five instructions in different stages of execution. In addition, the processor added: An 8-KByte on-chip first-level cache that increased the percent of instructions that could execute at the scalar rate of one per clock An integrated x87 FPU Power saving and system management capabilities 2.1.5 The Intel Pentium Processor (1993) The introduction of the Intel Pentium processor added a second execution pipeline to achieve superscalar performance (two pipelines, known as u and v, together can execute two instructions per clock). The on-chip first-level cache doubled, with 8 KBytes devoted to code and another 8 KBytes devoted to data. The data cache uses the MESI protocol to support more efficient write-back cache in addition to the writethrough cache previously used by the Intel486 processor. Branch prediction with an on-chip branch table was added to increase performance in looping constructs. 2-2 Vol. 1 INTEL 64 AND IA-32 ARCHITECTURES In addition, the processor added: Extensions to make the virtual-8086 mode more efficient and allow for 4-MByte as well as 4-KByte pages Internal data paths of 128 and 256 bits add speed to internal data transfers Burstable external data bus was increased to 64 bits An APIC to support systems with multiple processors A dual processor mode to support glueless two processor systems A subsequent stepping of the Pentium family introduced Intel MMX technology (the Pentium Processor with MMX technology). Intel MMX technology use...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.
- Winter '11