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Unformatted text preview: cendental instructions perform basic trigonometric and logarithmic operations on floating-point operands. FSIN FCOS FSINCOS FPTAN FPATAN F2XM1 FYL2X FYL2XP1 Sine Cosine Sine and cosine Partial tangent Partial arctangent 2x - 1 ylog2x ylog2(x+1) 5.2.5 x87 FPU Load Constants Instructions The load constants instructions load common constants, such as , into the x87 floating-point registers. FLD1 FLDZ FLDPI FLDL2E Load +1.0 Load +0.0 Load Load log2e 5-12 Vol. 1 INSTRUCTION SET SUMMARY FLDLN2 FLDL2T FLDLG2 Load loge2 Load log210 Load log102 5.2.6 x87 FPU Control Instructions The x87 FPU control instructions operate on the x87 FPU register stack and save and restore the x87 FPU state. FINCSTP FDECSTP FFREE FINIT FNINIT FCLEX FNCLEX FSTCW FNSTCW FLDCW FSTENV FNSTENV FLDENV FSAVE FNSAVE FRSTOR FSTSW FNSTSW WAIT/FWAIT FNOP Increment FPU register stack pointer Decrement FPU register stack pointer Free floating-point register Initialize FPU after checking error conditions Initialize FPU without checking error conditions Clear floating-point exception flags after checking for error conditions Clear floating-point exception flags without checking for error conditions Store FPU control word after checking error conditions Store FPU control word without checking error conditions Load FPU control word Store FPU environment after checking error conditions Store FPU environment without checking error conditions Load FPU environment Save FPU state after checking error conditions Save FPU state without checking error conditions Restore FPU state Store FPU status word after checking error conditions Store FPU status word without checking error conditions Wait for FPU FPU no operation 5.3 X87 FPU AND SIMD STATE MANAGEMENT INSTRUCTIONS
Save x87 FPU and SIMD state Restore x87 FPU and SIMD state Two state management instructions were introduced into the IA-32 architecture with the Pentium II processor family: FXSAVE FXRSTOR Vol. 1 5-13 INSTRUCTION SET SUMMARY Initially, these instructions operated only on the x87 FPU (and MMX) registers to perform a fast save and restore, respectively, of the x87 FPU and MMX state. With the introduction of SSE extensions in the Pentium III processor family, these instructions were expanded to also save and restore the state of the XMM and MXCSR registers. Intel 64 architecture also supports these instructions. See Section 10.5, "FXSAVE and FXRSTOR Instructions," for more detail. 5.4 MMXTM INSTRUCTIONS Four extensions have been introduced into the IA-32 architecture to permit IA-32 processors to perform single-instruction multiple-data (SIMD) operations. These extensions include the MMX technology, SSE extensions, SSE2 extensions, and SSE3 extensions. For a discussion that puts SIMD instructions in their historical context, see Section 2.2.4, "SIMD Instructions." MMX instructions operate on packed byte, word, doubleword, or quadword integer operands contained in memory, in MMX registers, and/or in general-purpose registers...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.
- Winter '11