ia-32_volume1_basic-arch

And the ferr and ignne pins as the intel486

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Unformatted text preview: depend on the order of actions by the x87 FPU exception handler to guarantee the correct hardware state upon exit from the handler. Flip Flop #2, which drives IGNNE# to the processor, has its CLEAR input attached to the inverted FERR#. This ensures that IGNNE# can never be active when FERR# is Vol. 1 D-7 GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS inactive. So if the handler clears the x87 FPU exception condition before the 0F0H access, IGNNE# does not get activated and left on after exit from the handler. 0F0H Address Decode Figure D-2. Behavior of Signals During x87 FPU Exception Handling D.2.1.3 No-Wait x87 FPU Instructions Can Get x87 FPU Interrupt in Window The Pentium and Intel486 processors implement the "no-wait" floating-point instructions (FNINIT, FNCLEX, FNSTENV, FNSAVE, FNSTSW, FNSTCW, FNENI, FNDISI or FNSETPM) in the MS-DOS compatibility mode in the following manner. (See Section 8.3.11, "x87 FPU Control Instructions," and Section 8.3.12, "Waiting vs. Non-waiting Instructions," for a discussion of the no-wait instructions.) If an unmasked numeric exception is pending from a preceding x87 FPU instruction, a member of the no-wait class of instructions will, at the beginning of its execution, assert the FERR# pin in response to that exception just like other x87 FPU instructions, but then, unlike the other x87 FPU instructions, FERR# will be de-asserted. This de-assertion was implemented to allow the no-wait class of instructions to proceed without an interrupt due to any pending numeric exception. However, the brief assertion of FERR# is sufficient to latch the x87 FPU exception request into most hardware interface implementations (including Intel's recommended circuit). All the x87 FPU instructions are implemented such that during their execution, there is a window in which the processor will sample and accept external interrupts. If there is a pending interrupt, the processor services the interrupt first before resuming the execution of the instruction. Consequently, it is possible that the nowait floating-point instruction may accept the external interrupt caused by it's own assertion of the FERR# pin in the event of a pending unmasked numeric exception, D-8 Vol. 1 GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS which is not an explicitly documented behavior of a no-wait instruction. This process is illustrated in Figure D-3. Exception Generating Floating-Point Instruction Assertion of FERR# by the Processor Start of the "No-Wait" Floating-Point Instruction System Dependent Delay Case 1 Assertion of INTR Pin by the System Case 2 Window Closed External Interrupt Sampling Window Figure D-3. Timing of Receipt of External Interrupt Figure D-3 assumes that a floating-point instruction that generates a "deferred" error (as defined in the Section D.2.1.1, "Basic Rules: When FERR# Is Generated"), which asserts the FERR# pin only on encountering the next floating-point instruct...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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