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Unformatted text preview: to set or clear this bit distinguishes an Intel386 processor from the later IA-32 processors. Bit 21 (ID) -- Determines if the processor is able to execute the CPUID instruction. The ability to set and clear this bit indicates that it is a Pentium 4, Intel Xeon, P6 family, Pentium, or later-version Intel486 processor. To determine whether an x87 FPU or NPX is present in a system, applications can write to the x87 FPU status and control registers using the FNINIT instruction and then verify that the correct values are read back using the FNSTENV instruction. After determining that an x87 FPU or NPX is present, its type can then be determined. In most cases, the processor type will determine the type of FPU or NPX; however, an Intel386 processor is compatible with either an Intel 287 or Intel 387 math coprocessor. The method the coprocessor uses to represent (after the execution of the FINIT, FNINIT, or RESET instruction) indicates which coprocessor is present. The Intel 287 math coprocessor uses the same bit representation for + and -; whereas, the Intel 387 math coprocessor uses different representations for + and -. 14-2 Vol. 1 APPENDIX A EFLAGS CROSS-REFERENCE
A.1 EFLAGS AND INSTRUCTIONS Table A-2 summarizes how the instructions affect the flags in the EFLAGS register. The following codes describe how the flags are affected. Table A-1. Codes Describing Flags
T M 0 1 -- R Blank Instruction tests flag. Instruction modifies flag (either sets or resets depending on operands). Instruction resets flag. Instruction sets flag. Instruction's effect on flag is undefined. Instruction restores prior value of flag. Instruction does not affect flag. Table A-2. EFLAGS Cross-Reference
Instruction AAA AAD AAM AAS ADC ADD AND ARPL BOUND BSF/BSR BSWAP BT/BTS/BTR/BTC CALL CBW -- -- -- -- -- M -- -- M -- -- -- OF -- -- -- -- M M 0 SF -- M M -- M M M ZF -- M M -- M M M M AF TM -- -- TM M M -- PF -- M M -- M M M CF M -- -- M TM M 0 TF IF DF NT RF Vol. 1 A-1 EFLAGS CROSS-REFERENCE Table A-2. EFLAGS Cross-Reference (Contd.)
Instruction CLC CLD CLI CLTS CMC CMOVcc CMP CMPS CMPXCHG CMPXCHG8B COMSID COMISS CPUID CWD DAA DAS DEC DIV ENTER ESC FCMOVcc FCOMI, FCOMIP, FUCOMI, FUCOMIP HLT IDIV IMUL IN INC INS INT INTO T 0 0 M M M M M T 0 0 -- M -- -- -- -- -- -- -- -- -- M T M T M T M -- -- M -- M M M -- M M M -- TM TM M -- M M M -- -- TM TM 0 0 0 0 T M M M T M M M T M M M M M M 0 0 M M M M M M M T M M M M T M M M T 0 OF SF ZF AF PF CF 0 0 TF IF DF NT RF A-2 Vol. 1 EFLAGS CROSS-REFERENCE Table A-2. EFLAGS Cross-Reference (Contd.)
Instruction INVD INVLPG UCOMSID UCOMISS IRET Jcc JCXZ JMP LAHF LAR LDS/LES/LSS/LFS/LGS LEA LEAVE LGDT/LIDT/LLDT/LMSW LOCK LODS LOOP LOOPE/LOOPNE LSL LTR MONITOR MWAIT MOV MOV control, debug, test MOVS MOVSX/MOVZX MUL NEG NOP NOT OR 0 M M -- M 0 M M -- M -- M -- M -- M M M -- -- -- -- -- -- T T M T M 0 0 R T 0 0 R T M M R T 0 0 R M M R T M M R T R R R T OF SF ZF AF PF CF TF IF DF NT RF Vol. 1 A-3 EFLAGS CROSS-REFERENCE Table A-2. EFLAGS Cross-Reference (C...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.
- Winter '11