ia-32_volume1_basic-arch

Are not supported and should not be used as operand

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Unformatted text preview: to memory in the destination format (floating point, integer, or packed BCD), then performs a pop operation on the register stack. A pop operation causes the ST(0) register to be marked empty and the stack pointer (TOP) in the x87 FPU control work to be incremented by 1. The FSTP instruction can also be used to copy the value in the ST(0) register to another x87 FPU register [ST(i)]. The FXCH (exchange register contents) instruction exchanges the value in a selected register in the stack [ST(i)] with the value in ST(0). The FCMOVcc (conditional move) instructions move the value in a selected register in the stack [ST(i)] to register ST(0) if a condition specified with a condition code (cc) is satisfied (see Table 8-5). The condition being tested for is represented by the Vol. 1 8-23 PROGRAMMING WITH THE X87 FPU status flags in the EFLAGS register. The condition code mnemonics are appended to the letters "FCMOV" to form the mnemonic for a FCMOVcc instruction. Table 8-5. Floating-Point Conditional Move Instructions Instruction Mnemonic FCMOVB FCMOVNB FCMOVE FCMOVNE FCMOVBE FCMOVNBE FCMOVU FCMOVNU Status Flag States CF=1 CF=0 ZF=1 ZF=0 CF=1 or ZF=1 CF=0 or ZF=0 PF=1 PF=0 Condition Description Below Not below Equal Not equal Below or equal Not below nor equal Unordered Not unordered Like the CMOVcc instructions, the FCMOVcc instructions are useful for optimizing small IF constructions. They also help eliminate branching overhead for IF operations and the possibility of branch mispredictions by the processor. Software can check if the FCMOVcc instructions are supported by checking the processor's feature information with the CPUID instruction. 8.3.4 Load Constant Instructions The following instructions push commonly used constants onto the top [ST(0)] of the x87 FPU register stack: FLDZ FLD1 FLDPI FLDL2T FLDL2E FLDLG2 FLDLN2 Load +0.0 Load +1.0 Load Load log2 10 Load log2e Load log102 Load loge2 The constant values have full double extended-precision floating-point precision (64 bits) and are accurate to approximately 19 decimal digits. They are stored internally in a format more precise than double extended-precision floating point. When loading the constant, the x87 FPU rounds the more precise internal constant according to the RC (rounding control) field of the x87 FPU control word. The inexactresult exception (#P) is not generated as a result of this rounding, nor is the C1 flag 8-24 Vol. 1 PROGRAMMING WITH THE X87 FPU set in the x87 FPU status word if the value is rounded up. See Section 8.3.8, "Pi," for information on the constant. 8.3.5 Basic Arithmetic Instructions The following floating-point instructions perform basic arithmetic operations on floating-point numbers. Where applicable, these instructions match IEEE Standard 754: FADD/FADDP FIADD FSUB/FSUBP FISUB FSUBR/FSUBRP FISUBR FMUL/FMULP FIMUL FDIV/FDIVP FIDIV FDIVR/FDIVRP FIDIVR FABS FCHS FSQRT FPREM FPREM1 FRNDINT FXTRACT Add floating point Add integer to floating point Su...
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