ia-32_volume1_basic-arch

Being signaled table 8 9 lists the non arithmetic and

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Invalid Arithmetic Operand Exception (#IA) The x87 FPU is able to detect a variety of invalid arithmetic operations that can be coded in a program. These operations are listed in Table 8-10. (This list includes the invalid operations defined in IEEE Standard 754.) When the x87 FPU detects an invalid arithmetic operand, it sets the IE flag (bit 0) in the x87 FPU status word to 1. If the invalid-operation exception is masked, the x87 FPU then returns an indefinite value or QNaN to the destination operand and/or sets the floating-point condition codes as shown in Table 8-10. If the invalid-operation exception is not masked, a software exception handler is invoked (see Section 8.7, "Handling x87 FPU Exceptions in Software") and the top-of-stack pointer (TOP) and source operands remain unchanged. Table 8-10. Invalid Arithmetic Operations and the Masked Responses to Them Condition Any arithmetic operation on an operand that is in an unsupported format. Any arithmetic operation on a SNaN. Ordered compare and test operations: one or both operands are NaNs. Masked Response Return the QNaN floating-point indefinite value to the destination operand. Return a QNaN to the destination operand (see Table 4-7). Set the condition code flags (C0, C2, and C3) in the x87 FPU status word or the CF, PF, and ZF flags in the EFLAGS register to 111B (not comparable). Return the QNaN floating-point indefinite value to the destination operand. Return the QNaN floating-point indefinite value to the destination operand. Return the QNaN floating-point indefinite value to the destination operand. Return the QNaN floating-point indefinite; clear condition code flag C2 to 0. Return the QNaN floating-point indefinite; clear condition code flag C2 to 0. Return the QNaN floating-point indefinite value to the destination operand. Store packed BCD integer indefinite value in the destination operand. Addition: operands are opposite-signed infinities. Subtraction: operands are like-signed infinities. Multiplication: by 0; 0 by . Division: by ; 0 by 0. Remainder instructions FPREM, FPREM1: modulus (divisor) is 0 or dividend is . Trigonometric instructions FCOS, FPTAN, FSIN, FSINCOS: source operand is . FSQRT: negative operand (except FSQRT (0) = 0); FYL2X: negative operand (except FYL2X (0) = ); FYL2XP1: operand more negative than 1. FBSTP: Converted value cannot be represented in 18 decimal digits, or source value is an SNaN, QNaN, , or in an unsupported format. 8-38 Vol. 1 PROGRAMMING WITH THE X87 FPU Table 8-10. Invalid Arithmetic Operations and the Masked Responses to Them (Contd.) FIST/FISTP: Converted value exceeds representable integer range of the destination operand, or source value is an SNaN, QNaN, , or in an unsupported format. FXCH: one or both registers are tagged empty. Store integer indefinite value in the destination operand. Load empty registers with the QNaN floatingpoint indefinite value, then perform the exchange. Normally, when one or both of the source operands...
View Full Document

This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

Ask a homework question - tutors are online