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Unformatted text preview: on 10.2, "SSE Programming Environment," for more information about these registers. Stack -- The stack pointer size is 64 bits. Stack size is not controlled by a bit in the SS descriptor (as it is in non-64-bit modes) nor can the pointer size be overridden by an instruction prefix. Control registers -- Control registers expand to 64 bits. A new control register (the task priority register: CR8 or TPR) has been added. See Chapter 2, "Intel 64 and IA-32 Architectures," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A. Debug registers -- Debug registers expand to 64 bits. See Chapter 18, "Debugging and Performance Monitoring," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B. Descriptor table registers -- The global descriptor table register (GDTR) and interrupt descriptor table register (IDTR) expand to 10 bytes so that they can 3-6 Vol. 1 BASIC EXECUTION ENVIRONMENT hold a full 64-bit base address. The local descriptor table register (LDTR) and the task register (TR) also expand to hold a full 64-bit base address. Basic Program Execution Registers Address Space 264 -1 Sixteen 64-bit Registers General-Purpose Registers Six 16-bit Registers 64-bits 64-bits FPU Registers Segment Registers RFLAGS Register RIP (Instruction Pointer Register) Eight 80-bit Registers Floating-Point Data Registers 0 16 bits 16 bits 16 bits 64 bits 64 bits MMX Registers Eight 64-bit Registers Control Register Status Register Tag Register Opcode Register (11-bits) FPU Instruction Pointer Register FPU Data (Operand) Pointer Register MMX Registers XMM Registers Sixteen 128-bit Registers 32-bits XMM Registers MXCSR Register Figure 3-2. 64-Bit Mode Execution Environment Vol. 1 3-7 BASIC EXECUTION ENVIRONMENT 3.3 MEMORY ORGANIZATION The memory that the processor addresses on its bus is called physical memory. Physical memory is organized as a sequence of 8-bit bytes. Each byte is assigned a unique address, called a physical address. The physical address space ranges from zero to a maximum of 236 - 1 (64 GBytes) if the processor does not support Intel 64 architecture. Intel 64 architecture introduces a changes in physical and linear address space; these are described in Section 3.3.3, Section 3.3.4, and Section 3.3.7. Virtually any operating system or executive designed to work with an IA-32 or Intel 64 processor will use the processor's memory management facilities to access memory. These facilities provide features such as segmentation and paging, which allow memory to be managed efficiently and reliably. Memory management is described in detail in Chapter 3, "Protected-Mode Memory Management," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A. The following paragraphs describe the basic methods of addressing memory when memory management is used. 3.3.1 IA-32 Memory Models When employing the processor's memory management facilities, programs do not directly addres...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.
- Winter '11