ia-32_volume1_basic-arch

Conditions 4 26 exception priority 4 30 inexact

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: masked response to, 8-38 Invalid operation exception (#I) overview, 4-26 SSE and SSE2 extensions, 11-20 x87 FPU, 8-36 IOPL (I/O privilege level) field EFLAGS register, 3-23, 13-4 IRET instruction, 3-24, 6-17, 6-18, 7-21, 7-31, 13-5 I/O address space, 13-2 instruction serialization, 13-7 instructions, 5-8, 7-27, 13-3 I/O privilege level (see IOPL) map base, 13-5 permission bit map, 13-5 ports, 3-5, 13-1, 13-2, 13-4, 13-7 sensitive instructions, 13-4 LOCK signal, 7-5 LODS instruction, 3-22, 7-26 Log epsilon, x87 FPU operation, 8-31 Logical address, 3-8 LOOP instructions, 7-23 LOOPcc instructions, 3-22, 7-23 LSS instruction, 7-31 M Machine check registers, 3-5 Machine specific registers (see MSRs) Maskable interrupts, 6-13 Masked responses denormal operand exception (#D), 4-26, 8-39 divide by zero exception (#Z), 4-27, 8-40 inexact result (precision) exception (#P), 4-30, 8-43 invalid arithmetic operation (#IA), 8-38 invalid operation exception (#I), 4-26 numeric overflow exception (#O), 4-28, 8-40 numeric underflow exception (#U), 4-29, 8-42 stack overflow or underflow exception (#IS), 8-37 MASKMOVDQU instruction, 11-17, 11-36 MASKMOVQ instruction, 10-18, 11-36 Masks, exception-flags MXCSR register, 10-6 x87 FPU control word, 8-11 MAXPD instruction, 11-9 MAXPS instruction, 10-12 MAXSD instruction, 11-9 MAXSS instruction, 10-12 Memory flat memory model, 3-8 management registers, 3-5 memory type range registers (MTRRs), 3-5 modes of operation, 3-10 organization, 3-8 physical, 3-8 real address mode memory model, 3-9, 3-10 segmented memory model, 3-8 virtual-8086 mode memory model, 3-9, 3-10 Memory operands 64-bit mode, 3-28 legacy modes, 3-28 Memory-mapped I/O, 13-2 MFENCE instruction, 11-17, 11-37 Microarchitecture (see Intel NetBurst microarchitecture) (see P6 family microarchitecture) MINPD instruction, 11-9 MINPS instruction, 10-13 MINSD instruction, 11-9 MINSS instruction, 10-13 MMX instruction set arithmetic instructions, 9-8 comparison instructions, 9-9 J J-bit, 4-14 Jcc instructions, 3-22, 3-24, 7-22 JMP instruction, 3-24, 7-20, 7-31 L L1 (level 1) cache, 2-7, 2-10 L2 (level 2) cache, 2-7, 2-10 LAHF instruction, 3-20, 7-29 Last instruction opcode, x87 FPU, 8-14 LDDQU instruction, 5-26, 12-4 LDMXCSR instruction, 10-17, 11-35 LDS instruction, 7-31 LDTR register, 3-5, 3-6 LEA instruction, 7-32 LEAVE instruction, 6-19, 6-26, 7-28 LES instruction, 7-31 LFENCE instruction, 11-17 LGS instruction, 7-31 Linear address, 3-8 Linear address space defined, 3-8 maximum size, 3-8 INDEX-8 Vol. 1 INDEX conversion instructions, 9-9 data transfer instructions, 9-8 EMMS instruction, 9-10 logical instructions, 9-10 overview, 9-6 shift instructions, 9-10 MMX registers description of, 9-3 overview of, 3-3 MMX technology 64-bit mode, 9-2 64-bit packed SIMD data types, 4-10 compatibility mode, 9-2 compatibility with FPU architecture, 9-10 data types, 9-3 detecting MMX technology with CPUID instruction, 9-11 effect of instruction prefixes on MMX instructions, 9-15 excepti...
View Full Document

This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

Ask a homework question - tutors are online