Data such as the display list in a 3 d graphics

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Unformatted text preview: OR instructions were introduced into the IA-32 architecture in the Pentium II processor family (prior to the introduction of the SSE extensions). The original versions of these instructions performed a fast save and restore, respectively, of the x87 FPU register state. (By saving the state of the x87 FPU data registers, the FXSAVE and FXRSTOR instructions implicitly save and restore the state of the MMX registers.) The SSE extensions expanded the scope of these instructions to save and restore the states of the XMM registers and the MXCSR register, along with the x87 FPU and MMX state. The FXSAVE and FXRSTOR instructions can be used in place of the FSAVE/FNSAVE and FRSTOR instructions; however, the operation of the FXSAVE and FXRSTOR instructions are not identical to the operation of FSAVE/FNSAVE and FRSTOR. 10-20 Vol. 1 PROGRAMMING WITH STREAMING SIMD EXTENSIONS (SSE) NOTE The FXSAVE and FXRSTOR instructions are not considered part of the SSE instruction group. They have a separate CPUID feature bit to indicate whether they are present (if CPUID.01H:EDX.FXSR[bit 24] = 1). The CPUID feature bit for SSE extensions does not indicate the presence of FXSAVE and FXRSTOR. 10.6 HANDLING SSE INSTRUCTION EXCEPTIONS See Section 11.5, "SSE, SSE2, and SSE3 Exceptions," for a detailed discussion of the general and SIMD floating-point exceptions that can be generated with the SSE instructions and for guidelines for handling these exceptions when they occur. 10.7 WRITING APPLICATIONS WITH THE SSE EXTENSIONS See Section 11.6, "Writing Applications with SSE/SSE2 Extensions," for additional information about writing applications and operating-system code using the SSE extensions. Vol. 1 10-21 PROGRAMMING WITH STREAMING SIMD EXTENSIONS (SSE) 10-22 Vol. 1 CHAPTER 11 PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2) The streaming SIMD extensions 2 (SSE2) were introduced into the IA-32 architecture in the Pentium 4 and Intel Xeon processors. These extensions enhance the performance of IA-32 processors for advanced 3-D graphics, video decoding/encoding, speech recognition, E-commerce, Internet, scientific, and engineering applications. This chapter describes the SSE2 extensions and provides information to assist in writing application programs that use these and the SSE extensions. 11.1 OVERVIEW OF SSE2 EXTENSIONS SSE2 extensions use the single instruction multiple data (SIMD) execution model that is used with MMX technology and SSE extensions. They extend this model with support for packed double-precision floating-point values and for 128-bit packed integers. If CPUID.01H:EDX.SSE2[bit 26] = 1, SSE2 extensions are present. SSE2 extensions add the following features to the IA-32 architecture, while maintaining backward compatibility with all existing IA-32 processors, applications and operating systems. Six data types: -- 128-bit packed double-precision floating-point (two IEEE Standard 754 double-precision floating-point values packed into a doub...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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